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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 ADM1029 * dual pwm fan controller and temperature monitor for high availability systems functional block diagram fan 2 status register interrupt masking interrupt mask registers bandgap reference analog mux bandgap temp sensor adc add ain0/gpio0 remote sensor signal conditioning g.p. i/o register value and limit registers ain1/gpio1 d1+/gpio4 d1?gpio3 limit comparator tach1 tach2 fault2 present2 fault1 present1 drive1 drive2 fan speed counter address pointer register gnd int cfault d2?gpio5 d2+/gpio6 reset gpio2 tmin/install fan 1 status register slave address register serial bus interface scl sda v cc interrupt status registers fan 1 alarm speed register fan 1 min speed register pwm controller fan 1 hot-plug speed register fan 2 hot-plug speed register fan 2 alarm speed register fan 2 min speed register pwm controller ADM1029 features software programmable and automatic fan speed control automatic fan speed control allows control independent of cpu intervention after initial setup control loop minimizes acoustic noise and power consumption remote and local temperature monitoring dual fan speed measurement supports backup and redundant fans supports hot swapping of fans cascadable fault output allows fault signaling between multiple ADM1029s address pin allows up to eight ADM1029s in a system small 24-lead qsop package applications network servers and personal computers microprocessor-based office equipment high availability telecommunications equipment * protected by u.s. patent numbers 6,255,973 and 6,188,189
rev. 0 C2C ADM1029?pecifications 1, 2 (t a = t min to t max , v cc = v min to v max , unless otherwise noted.) parameter min typ max unit test conditions/comments power supply supply voltage, v cc 3.0 3.30 5.5 v supply current, i cc 1.7 3.0 ma interface inactive, adc active 1.5 ma adc inactive, dac active 10 60 a shutdown mode temperature-to-digital converter internal sensor accuracy 1 3 c resolution 1 c external diode sensor accuracy 3 5 c0 c t a 100 c resolution 1 c remote sensor source current 90 a high level 5.5 a low level analog-to-digital converter total unadjusted error, tue 1 % note 3 differential nonlinearity, dnl 1 lsb power supply sensitivity 1 %/ v conversion time analog input or internal temperature 11.6 ms external temperature 185.6 ms fan rpm-to-digital converter accuracy 6%60 c t a 100 c: v cc = 3.3 v full-scale count 255 fan 1 and fan 2 nominal input rpm 4 8800 rpm divisor = 1, fan count = 153 4400 rpm divisor = 2, fan count = 153 2200 rpm divisor = 4, fan count = 153 1100 rpm divisor = 8, fan count = 153 internal clock frequency 56.4 60.0 63.6 khz open-drain digital outputs ( int , cfault ) output low voltage, v ol 0.4 v i out = C6.0 ma, v cc = 3 v high level output current, i oh 0.1 1 av out = v cc open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = C6.0 ma, v cc = 3 v high level output leakage current, i oh 0.1 1 av out = v cc serial bus digital inputs (scl, sda) input high voltage, v ih 2.1 v input low voltage, v il 0.8 v hysteresis 500 mv digital input logic levels reset , gpio1-6, fault1/2, tach1/2, present1/2 input high voltage, v ih 2.1 v input low voltage, v il 0.8 v digital input current input high current, i ih C1 av in = v cc input low current, i il +1 av in = 0 input capacitance, c in 20 pf serial bus timing 5 clock frequency, f sclk 10 100 khz see figure 1 glitch immunity, t sw 50 ns see figure 1 bus free time, t buf 4.7 s see figure 1 start setup time, t su:sta 4.7 s see figure 1 start hold time, t hd:sta 4 s see figure 1 stop condition setup time, t su:sto 4 s see figure 1 rev. 0 C3C ADM1029 parameter min typ max unit test conditions/comments serial bus timing 5 (continued) scl low time, t low 1.3 s see figure 1 scl high time, t high 450 s see figure 1 scl, sda rise time, t r 1000 ns see figure 1 scl, sda fall time, t f 300 ns see figure 1 data setup time, t su:dat 250 ns see figure 1 data hold time, t hd:dat 300 ns see figure 1 notes 1 all voltages are measured with respect to gnd, unless otherwise speci?ed. 2 typicals are at t a = 25 c and represent most likely parametric norm. shutdown current typ is measured with v cc = 3.3 v. 3 tue (total unadjusted error) includes offset, gain, and linearity errors of the adc, multiplexer. 4 the total fan count is based on two pulses per revolution of the fan tachometer output. 5 timing speci?cations are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.1 v for a rising edge. speci?cations subject to change without notice. absolute maximum ratings * positive supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . 6.5 v voltage on pins 13C18 . . . . . . . . . . . . C0.3 v to (v cc + 0.3 v) voltage on any o ther input or output pin . . . . C0.3 v to +6.5 v input current at any pin . . . . . . . . . . . . . . . . . . . . . . . 5 ma package input current . . . . . . . . . . . . . . . . . . . . . . . 20 ma maximum junction temperature (t j max) . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 c esd rating all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 v * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration ADM1029 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 drive1 fault1 tach1 present1 scl sda gnd v cc cfault int gpio2 reset drive2 fault2 tach2 present2 ain1/gpio1 ain0/gpio0 tmin/install d2+/gpio6 d2 /gpio5 add d1+/gpio4 d2 /gpio3 thermal characteristics 24-lead qsop package: ja = 105 c/w, jc = 39 c/w ordering guide temperature package package model range description option ADM1029arq 0 c to 100 c shrink small outline rq-24 package (qsop) p s s p t hd;sta t hd;dat t high t su;dat t su;sta t su;sto t low t r t f t hd;sta scl sda t buf figure 1. diagram for serial bus timing rev. 0 ADM1029 C4C pin function descriptions pin no. mnemonic description 1 drive1 open drain digital output. pulsewidth modulated (pwm) output to control the speed of fan 1. requires 10 k ? typical pull-up resistor. 2 fault1 open drain digital i/o. when used with a fan having a fault output, a logic 0 input to this pin signals a fault on fan 1. also used as a fault output. 3 tach1 open drain digital input. digital fan tachometer input for fan 1. will accept logic signals up to 5 v even when v cc is lower than 5 v. 4 present1 open drain digital input. a shorting link in the fan connector holds this pin low when fan 1 is connected. 5 scl open drain digital input. serial bus clock. requires 2.2 k ? pull-up typical. 6 sda digital i/o. serial bus bidirectional data. open-drain output requires 2.2 k ? pull-up. 7 gnd system ground 8v cc power (3.0 v to 5.5 v). typically powered from 3.3 v power rail. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. 9 cfault open drain digital i/o. cascade fault input/output used for fault signaling between multiple ADM1029s. 10 int digital output. interrupt request (open drain). the output is enabled when bit 1 of the configuration register is set to 0. the default state is enabled. 11 gpio2 open drain digital i/o. general-purpose logic i/o pin. 12 reset open drain digital input. active low reset input. 13 d1C/gpio3 analog input/open drain digital i/o. connected to cathode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 14 d1+/gpio4 analog input/open drain digital i/o. connected to anode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 15 add eight-level analog input. used to set the three lsbs of the serial bus address. 16 d2C/gpio5 analog input/open drain digital i/o. connected to cathode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 17 d2+/gpio6 analog input/open drain digital i/o. connected to anode of external temperature-sensing diode, or may be reconfigured as a general-purpose logic input/output. 18 tmin/install eight-level analog input. the voltage on this pin defines whether automatic fan speed control is enabled, the minimum temperature at which the fan(s) will turn on in automatic speed con- trol mode, and the number of fans that should be installed. 19 ain0/gpio0 analog input/open drain digital i/o. may be configured as a 0 v to 2.5 v analog input or as a general-purpose digital i/o pin. 20 ain1/gpio1 analog input/open drain digital i/o. may be configured as a 0 v to 2.5 v analog input or as a general-purpose digital i/o pin. 21 present2 open drain digital input. a shorting link in the fan connector holds this pin low when fan 2 is connected. 22 tach2 open drain digital input. digital fan tachometer input for fan 2. will accept logic signals up to 5 v even when v cc is lower than 5 v. 23 fault2 open drain digital i/o. when used with a fan having a fault output, a logic 0 input to this pin signals a fault on fan 2. also used as a fault output. 24 drive2 open drain digital output. pulsewidth modulated (pwm) output to control the speed of fan 2. requires 10 k ? typical pull-up resistor. rev. 0 C5C typical performance characteristics ADM1029 15 10 5 0 5 10 15 20 0 3.3 10 30 100 remote temperature error c leakage resistance m dxp to gnd dxp to v cc (3.3v) tpc 1. remote temperature error vs. pc board track resistance 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 0 1 4 8 12 16 20 50 100 200 300 400 500 600 remote temperature error c frequency mhz v in = 100mv p-p v in = 250mv p-p tpc 2. remote temperature error vs. power supply noise frequency 10 9 8 7 6 5 4 3 2 1 0 1 0 0.4 0.8 10 600 150 400 50 250 500 100 200 350 450 550 300 remote temperature error c frequency mhz v in = 40mv p-p v in = 60mv p-p v in = 100mv p-p tpc 3. remote temperature error vs. common-mode noise frequency 110 100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 reading measured temperature *-.+ - 3 * 2 2'$4 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1.0 2.2 3.3 4.7 10.0 22.0 47.0 remote temperature error c dxp dxn capacitance nf *-., * . ) 5 # 80 70 60 50 40 30 20 10 0 0 1 5 10 25 50 75 100 250 500 750 1000 supply current a sclk frequency khz v cc = 5v v cc = 3.3v tpc 6. standby current vs. clock frequency pentium is a registered trademark of intel corporation. rev. 0 ADM1029 C6C 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 600 12 400 20 300 100 500 1 4 8 16 50 200 remote temperature error c frequency mhz v in = 30mv p-p v in = 20mv p-p v in = 40mv p-p tpc 7. remote temperature error vs. differential-mode noise frequency 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 supply current a supply voltage v 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 tpc 8. standby supply current vs. supply voltage 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 supply current ma supply voltage v tpc 9. supply current vs. supply voltage 10 9 8 7 6 5 4 3 2 1 0 1 0 1 4 8 12 16 20 50 100 200 300 400 500 600 local temperature error c frequency mhz v in = 100mv p-p v in = 250mv p-p tpc 10. local sensor temperature error vs. power supply noise frequency 120 110 100 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 temperature c time seconds tpc 11. ADM1029 response to thermal shock error c temperature c 0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 0 20 40 60 80 85 100 105 120 tpc 12. remote temperature error rev. 0 ADM1029 C7C table i. resistor ratios for setting serial bus address 3 msbs ideal ratio r1 r2 actual error of adc r2/(r1 + r2) (k )(k ) r2/(r1 + r2) % address 111 n/a 0 1 0 0101111 110 0.8125 18 82 0.82 +0.75 0101110 101 0.6875 22 47 0.6812 C0.63 0101101 100 0.5625 12 15 0.5556 C0.69 0101100 011 0.4375 15 12 0.4444 +0.69 0101011 010 0.3125 47 22 0.3188 +0.63 0101010 001 0.1875 82 18 0.18 C0.75 0101001 000 n/a 0 0 0 0101000 error c temperature c 0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0 20 40 60 80 85 100 105 120 tpc 13. local temperature error product description the ADM1029 is a versatile fan controller and monitor for use in personal computers, servers, telecommunications equipment, or any high-availability system where reliable control and moni- toring of multiple cooling fans is required. each ADM1029 can control the speed of one or two fans and can measure the speed of fans that have a tachometer output. the ADM1029 can also measure the temperature of one or two external sensing diodes or an internal temperature sensor, allowing fan speed to be adjusted to keep system temperature within acceptable limits. the ADM1029 has fault inputs for use with fans that can signal failure conditions, and inputs to detect whether or not fans are connected. the ADM1029 communicates with the host processor over an system manag ement (smbus) serial bus. it supports eight diff erent serial bus addresses, so that up to eight devices can be connected to a common bus, controlling up to sixteen fans. this makes software support and hardware design scalable. the ADM1029 has an interrupt output ( int ) that allows it to signal fault conditions to the host processor. it also has a separate, cascadable fault output ( cfault ) that allows the ADM1029 to signal a fault condition to other ADM1029s. the ADM1029 has a number of useful features including an auto matic fan speed control option implemented in hardware with no software requirement, automatic use of backup fans in the event of fan failure, and supports hot-swapping of failed fans. functional description serial bus interface control of the ADM1029 is carried out via the serial bus. the ADM1029 is connected to this bus as a slave device, under the control of a master device. the ADM1029 has a 7-bit serial bus address. the four msbs of the add ress are set to 0101. the three lsbs can be set by the user to give a total of eight different addresses, allowing up to eight ADM1029s to be connected to a single serial bus segment. to minimize device pin count and size, the three lsbs are set using a single pin (add, pin 15). this is an 8-level input whose input voltage is set by a potential divider. the voltage on add is sampled immediately after power-up and digitized by the on-chip adc to determine the value of the 3 lsbs. since add is sampled only at power-up, any changes made while power is on will have no effect. ADM1029 add v cc gnd r1 r2 figure 2. setting the serial address table i shows resistor values for setting the 3 lsbs of the serial bus address. the same principle is used to set the voltage on pin 18 (tmin/install), which controls the automatic fan speed control function, and also tells the ADM1029 how many fans should be installed, as described later. if several ADM1029s are used in a system, their add inputs can tap off a single potential divider, as shown in figure 3. add add add add add add add add address xxxx000 address xxxx001 address xxxx111 address xxxx110 address xxxx101 address xxxx100 address xxxx011 address xxxx010 v cc gnd 1.5k 1k 1k 1k 1k 1k 1.5k ADM1029 #1 ADM1029 #2 ADM1029 #3 ADM1029 #4 ADM1029 #5 ADM1029 #6 ADM1029 #7 ADM1029 #8 figure 3. setting address of up to eight ADM1029s rev. 0 ADM1029 C8C r/ w 0 scl sda 10 1 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by ADM1029 start by master frame 1 serial bus address byte frame 2 address pointer register byte 191 ack. by ADM1029 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by ADM1029 stop by master frame 3 data byte 1 9 scl (continued) sda (continued) figure 4a. writing a register address to the address pointer register, then writing data to the selected register r/ w 0 scl sda 10 1 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by ADM1029 stop by master start by master frame 1 serial bus address byte frame 2 address pointer register byte 191 ack. by ADM1029 9 figure 4b. writing to the address pointer register only r/ w 0 scl sda 10 1 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. by master stop by master start by master frame 1 serial bus address byte frame 2 data byte from ADM1029 191 ack. by ADM1029 9 figure 4c. reading data from a previously selected register the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda, while the serial clock line scl remains high. this indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit, which deter- mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowl- edge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, the master will write to the slave device. if the r/ w bit is a 1 the master w ill read from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. when all data bytes have been read or written, stop condi- tions are established. in write mode, the master will pull the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the tenth clock pulse, high during the tenth clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. rev. 0 ADM1029 C9C in the case of the ADM1029, write operations contain either one or two bytes, and read operations contain one byte, and perform the following functions: to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, data can be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer r egis- ter. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this is illustrated in figure 4a. the device address is sent over the bus followed by r/ w set to 0. this is followed by two data bytes. the first data byte is the address of the internal data regis ter to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. when reading data from a register there are two possibili ties: 1. if the ADM1029s address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. this is done by performing a write to the ADM1029 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. this is shown in figure 4b. a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte read from the data register. this is shown in figure 4c. 2. if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so figure 4b can be omitted. note: although it is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. alert response address the ADM1029 has an interrupt ( int ) output that is asserted low when a fault condition occurs. several int outputs can be wire ord to a common interrupt line. when the host processor receives an interrupt request, it would normally need to read the interrupt status register of each device to identify which de vice had m ade the interrupt request. however, the ADM1029 sup- ports the optional alert response address function of the smbus protocol. w hen the host processor receives an interrupt request it can send a general call address (0001100) over the bus. the device asserting int will then send its own slave address back to the host processor, so the device asserting int can be identi- fied immediately. if more than one device is asserting int , all devices will try to respond with their slave address, but an arbitration process ensures that only the lowest address will be received by the host. after sending its slave address, the first device will then clear its int output. the host can then check if the int is still low and send the general call again if necessary until all devices asserting int have responded. the ara function can be disabled by setting bit 2 of the con- figuration register (address 01h). temperature measurement system local temperature measurement the ADM1029 contains an on-chip bandgap temperature sensor, whose output is digitized by the on-chip adc. the temperature data is stored in the local temp value register (address a0h). as both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in table ii. theoretically, the temperature sensor and adc can measure temperatures from C128 c to +127 c with a resolution of 1 c, but temperatures outside the operating temperature range of the device cannot be measured by the internal sensor. remote temperature measurement the ADM1029 can measure the temperature of one or two remote diode-connected transistors, connected to pins 13 and 14 and/or 16 and 17. the data from the temperature measure- ments is stored in the remote 1 and remote 2 temp value registers (addresses a1h and a2h). if two remote temperature measurements are not required, pins 16 and 17 can be reconfigured as general-purpose logic i/o pins, as explained later. the forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about C2 mv/ c. the absolute value of v be varies from device to device and individual calibration is required to null this out so, unfor tunately, the technique is unsu itable for mass production. the technique used in the ADM1029 is to measure the change in v be when the device is operated at two different currents. this is given by: ? v be = kt / q ln( n ) where: k is boltzmanns constant q is charge on the carrier t is absolute temperature in kelvins n is ratio of the two currents figure 5 shows the input signal conditioning used to measure the output of a remote temperature sensor. this figure shows the external sensor as a substrate transi stor, provided for tem- perature monitoring on some microprocessors, but it could equally well be a discrete transistor. if a discrete transistor is used, the collector will not be grounded, and should be linked to the base. if a pnp transistor is used, the base is connected to the dC input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the dC input and the base to the d+ input. rev. 0 ADM1029 C10C d+ d remote sensing transistor low-pass filter f c = 65khz v dd to adc v out + v out i n i i bias bias diode figure 5. signal conditioning for remote diode temperature sensors temperature limits the contents of the local and remote temperature value regis- ters (addresses a0h to a2h) are compared to the contents of the high and low limit registers at addresses 90h to 92h and 98h to 9ah. how the ADM1029 responds to overtemperature/ undertemperature conditions depends on the status of the tem- perature fault action registers (addresses 40h to 42h). the response of cfault , int , and fan-speed-to-temperature events depends on the setting of these registers, as explained later. table ii. temperature data format temperature digital output C128 c 1000 0000 C125 c 1000 0011 C100 c 1001 1100 C75 c 1011 0101 C50 c 1100 1110 C25 c 1110 0111 0 c 0000 0000 +10 c 0000 1010 +25 c 0001 1001 +50 c 0011 0010 +75 c 0100 1011 +100 c 0110 0100 +125 c 0111 1101 +127 c 0111 1111 to prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but biased above ground by an internal diode at the dC input. if the sensor is used in a noisy environment, a capacitor of value up to 1000 pf may be placed between the d+/dC pins. to measure ? v be , the sensor is switched between operating currents of i and n i. the resulting waveform is passed through a 65 khz low-pass filter to remove noise, and to a chopper-stabilized amplifier that performs the fun ctions of amplification and rectif ication of the waveform to produce a dc voltage proportional to ? v be . this voltage is measured by the adc to give a temperature output in 8-bit twos complement format. to further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. an external temperat ure measurement takes nominally 9.6 ms. the results of external temperature measurements are stored in 8-bit, twos complement format, as illustrated in table ii. offset registers digital noise and other error sources can ca use offset errors in the temperature measurement, particularly on the remote sen- sors. the ADM1029 offers a way to minimize these effects. the offsets on the three temperature channels can be measured during system characterization and stored as twos complement values in three offset registers at addresses 30h to 32h. the offset values are automatically added to, or subtracted from, the tem- perature values, depending on whether the twos complement number corresponds to a positive or negative offset. offset val- ues from C15 c to +15 c are allowed. the default value in the offset registers is zero, so if no offsets are programmed, the temperature measurements are unaltered. rev. 0 ADM1029 C11C table iii. temperature-specific registers address description 0x06 temp devices installed 0x30 local temp offset 0x31 remote 1 temp offset 0x32 remote 2 temp offset 0x40 local temp fault action 0x41 remote 1 temp fault action 0x42 remote 2 temp fault action 0x48 local temp cooling action 0x49 remote 1 temp cooling action 0x4a remote 2 temp cooling action 0x80 local temp tmin 0x81 remote 1 temp tmin 0x82 remote 2 temp tmin 0x88 local temp trange/thyst 0x89 remote 1 temp trange/thyst 0x8a remote 2 temp trange/thyst 0x90 local temp high limit 0x91 remote 1 temp high limit 0x92 remote 2 temp high limit 0x98 local temp low limit 0x99 remote 1 temp low limit 0x9a remote 2 temp low limit 0xa0 local temp value 0xa1 remote 1 temp value 0xa2 remote 2 temp value the flowchart in figure 7 shows how to configure the ADM1029 to measure temperature. it also shows how to configure the ADM1029s behavior for out-of-limit temperature measurements. fan interfacing the ADM1029 can be interfaced to many types of fan. it can be used to control the speed of a simple two-wire fan. it can mea- sure the speed of a fan with a tach output, and it can accept a logic input from fans with a fault output. by means of a shorting link in the fan connector it can also determine if a fan is present or not and if fans have been hot-swapped. the ADM1029 can control or monitor one or two fans. bits 0 and 1 of the fans supported in system register (03h) tell the ADM1029 how many fans it should be controlling/monitoring. in the following descriptions installed means that the corre- sponding bit of register 03h is set and the ADM1029 expects to see a fan interfaced to it. it does not necessarily mean that the fan is actually, physically, connected. if a fan is installed, events such as a fault output and hot-swapping of the fan can cause int and cfault to be asserted, unless they are masked for that particular event. if a fan is not installed, but is still physically connected to the ADM1029, these events will be ignored with respect to asserting int or cfault , but will still be reflected in the corresponding fan status register. setting bit 0 indicates that fan 1 is installed and is set to 1 at power-up by default. setting bit 1 indicates that fan 2 is installed and depends on the state of pin 18 (tmin/install) at power-up. layout considerations digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particu- larly when measuring the very small voltages from a remote diode sensor. the following precautions should be taken: 1. place the ADM1029 as close as possible to the remote sens- ing diode. provided that the worst noise sources such as clock generators, data/address buses, and crts are avoided, this distance can be 4 to 8 inches. 2. route the d+ and dC tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. 3. use wide tracks to minimize inductance and reduce noise pickup. ten mil track minimum width and spacing is recommended. gnd d+ d gnd 10mil 10mil 10mil 10mil 10mil 10mil 10mil figure 6. arrangement of signal tracks 4. try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and dC path and at the same temperature. thermocouple effects should not be a major problem as 1 c corresponds to about 240 v, and thermocouple voltages are about 3 v/ o c of temperature difference. unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 v. 5. place 0.1 f bypass and 1000 pf input filter capacitors close to the ADM1029. 6. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. this will work up to about 6 to 12 feet. 7. for really long distances (up to 100 feet), use shielded twisted pair such as belden #8451 microphone cable. con- nect the twisted pair to d+ and dC and the shield to gnd close to the ADM1029. leave the remote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor may be reduced or removed. cable resistance can also introduce errors. 1 ? series resistance introduces about 0.5 c error. temperature-related registers table iii is a list of registers on the ADM1029 that are specific to temperature measurement and control. rev. 0 ADM1029 C12C automatic fan speed control (see table x later) bit 0 = 1 fan 1 runs at alarm speed for out-of-limit temperature events; otherwise, fan 1 runs at speed determined by automatic fan control. bit 1 = 1 fan 2 runs at alarm speed for out-of-limit temperature events; otherwise, fan 2 runs at speed determined by automatic fan control. xxxxxx1 0 bit 0 = 1 assert cfault on over-temperature bit 1 = 1 run fan(s) alarm speed on over-temperature bit 2 = 1 assert int on over-temperature bit 3 = 0 alarm below low temp limit bit 3 = 1 alarm above low temp limit bit 4 = 1 assert cfault when low temp limit crossed bit 5 = 1 run fan alarm speed on under-temperature bit 6 = 1 assert int on under-temperature bit 7 latches a temperature out-of-limit event 7 6 5 4 3 2 1 0 measure temperature local (reg 0xa0) remote 1 (reg 0xa1) remote 2 (reg 0xa2) configure temperature high limits local (reg 0x90) remote 1 (reg 0x91) remote 2 (reg 0x92) defaults local = 80 c remote 1 = 100 c remote 2 = 100 c configure temperature low limits local (reg 0x98) remote 1 (reg 0x99) remote 2 (reg 0x9a) defaults local = 60 c remote 1 = 70 c remote 2 = 70 c configure temperature offsets local (reg 0x30) remote 1 (reg 0x31) remote 2 (reg 0x32) defaults local = 0 c remote 1 = 0 c remote 2 = 0 c configure temperature cooling action local (reg 0x48) remote 1 (reg 0x49) remote 2 (reg 0x4a) configure temperature fault action local (reg 0x40) remote 1 (reg 0x41) remote 2 (reg 0x42) is temperature > high limit? cfault yes is temperature > high limit? yes fans run alarm speed is temperature > high limit? yes int alarm above or below low temp limit? 0 = alarm below temp limit 1 = alarm above temp limit low temp limit crossed? cfault yes low temp limit crossed? yes fans run alarm speed low temp limit crossed? yes int figure 7. temperature sensing flowchart rev. 0 ADM1029 C13C if two fans are installed, bit 0 would be 1 by default and pin 18 would be tied high * to set bit 1. if only one fan is installed, it would normally be fan 1 and pin 18 would be tied low * to clear bit 1. however, both of these bits can be modified by writing to the register, so it is possible to have fan 2 installed and not fan 1, or even have no fans installed. * note that pin 18 also sets tmin for automatic fan speed control. if this function is used, pin 18 would be set to some other level according to table viii. fault inputs/outputs the ADM1029 can be used with fans that have a fault output which indicates if the fan has stalled or failed. if one or both of the fault inputs (pin 2 or pin 23) goes low, both int and cfault will be asserted. events on the fault inputs are also reflected in bits 2 and 3 of the corresponding fan status registers at addresses 10h and 11h. bit 2 reflects the inverse state of the fault pin (0 if fault is high, 1 if fault is low), while bit 3 is latched high if a fault input goes low. it must be cleared by writing a zero to it. if the fan(s) being used do not have a fault output, the fault input(s) on the ADM1029 should be pulled high to v cc . the fault pins can also be configured as open-drain outputs by setting bit 5 of the corresponding fan fault action register (18h or 19h). if a fault pin is configured as an output, it will still function as an input. this means that when a fault input occurs it will be latched low by the fault output, even if the fault input is removed. the fault output can be used to drive a fan failure indicator such as an led. if the fault pin is used as an output, any input to the fault pin should also be open-drain. this will avoid the fault input trying to source a high current into the fault pin if the fault input goes high while the fault output is low. fan present inputs the fan present signal is implemented by a shorting link to ground in the fan connector. when the fan is plugged in, the corresponding present input (pin 4 or pin 21) on the ADM1029 is pulled low. if the fan is unplugged, the present input will be pulled high. int and cfault will be asserted (unless masked) and the event will be reflected in bits 0 and bit 1 of the corresponding fan status register. appearance or disappearance of a present input signal dur- ing normal operation signals to the ADM1029 that a fan has been ho t-plugged or unplugged. int and cfault will be asserted (unless masked). when a fan is hot-plugged, bit 7 of the corresponding fan status register will be set and a fan free wheel test commences automatically. fan speed measurement the fan counter does not count the fan tach output pulses directly, because at low fan speeds it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on- chip oscillator into the input of an 8-bit counter. the fan speed measuring circuit is initialized on the first rising edge of a fan tach pulse after monitoring is enabled by setting bit 4 of the configuration register. it then starts counting on the rising edge of the second tach pulse and counts for four fan tach periods, until the rising edge of the sixth tach pulse, or until the counter overranges if the fan tach period is too long. after the speed of the first fan has been measured, the speed of the second fan (if installed) will be measured in the same way. the measurement cycle will repeat until monitoring is disabled. the fan speed measurements are stored in the fan tach value registers at addresses 70h and 71h. if both fans are installed, fan 1 will be measured first. if only one fan is installed, the ADM1029 will still try to m easure both fans, starting with fan 1, but the measurement on the noninstalled fan will time out when the fan tach value count overranges. the fan speed count is given by: count = f 4 60/ r/n where: f is oscillator frequency in hz factor 4 is because 4 tach periods are counted factor 60 is to convert minutes to seconds r = fan speed in rpm n is number of tach pulses per revolution the frequency of the oscillator can be adjusted to suit the expected frequency range of the fan tach pulses, which depends on the fan speed and the number of tach pulses produced for each revolution of the fan, which is either 1, 2, or 4. the oscillator frequency is set by bits 7 and 6 of the fan configuration regis- ters (68h for fan 1 and 69h for fan 2). table iii. oscillator frequencies bit 7 bit 6 oscillator frequency (hz) 0 0 measurement disabled 0 1 470 1 0 940 1 1 1880 clock config reg. bit 4 fan 1 tach fan 1 measurement period fan 2 measurement period start of monitoring cycle fan 2 tach figure 8. fan speed measurement fan speed limits fans generally do not overspeed if run from the correct voltage, so the failure condition of interest is under-speed due to electri- cal or mechanical failure. for this reason only low-speed limits are programmed into the tach limit registers for the fans. these registers are at address 78h for fan 1 and 79h for fan 2. it should be noted that, since fan period rather than speed is being measured, the fan speed count will be larger the slower the fan speed. therefore a fan failure fault will occur when the measurement exceeds the limit value. rev. 0 ADM1029 C14C for the most accurate fan failure indication, the oscillator frequ ency should be chosen to give as large a limit value as possible without the counter overranging. a count close to 3/4 full-scale or 191 is the optimum value. for example, if a fan produces two tach pulses per revol ution and the fan failure speed is to be 600 rpm, the oscillator fre- quency should be set to 940 hz. this will give a count at the fail speed of: 940 4 60/600/2 = 188 if the oscillator frequency were only 470 hz, the count would be 94, while an oscillator frequency of 1880 hz cannot be used because the count would be 376 and the counter would overrange. fan monitoring cycle time five complete tach periods are required to carry out a fan speed measurement therefore, if the start of a fan measurem ent just misses a rising edge, the measurement can take almost six tach periods for each fan. the worst-case monitoring cycle time is when both fans are under speed and the fan speed counter counts up to its maxi- mum value. the actual count takes 256 oscillator pulses over four tach periods, plus a further two tach periods or 128 oscilla- tor pulses before the count starts. the total monitoring cycle time is therefore: t meas = 384/ f osc ( fan 1) + 384/ f osc ( fan 2) in order to read a valid result from the fan tach value registers, the total monitoring time allowed after starting the monitoring cycle should be greater than this. tach signal conditioning signal conditioning in the ADM1029 accommodates the slow rise and fall times typical of fan tachometer outputs. the maxi- mum input signal range is 0 v to 5 v, even if v cc is less than 5 v. in the event that these inputs are supplied from fan outputs that exceed 0 v to 5 v, either r esistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figures 9a to 9d show circuits for most common fan tach outputs. if the fan tach output has a resistive pull-up to v cc , it can be connected directly to the fan input, as shown in fi gure 9a. 12v fan speed counter tach1 or tach2 pull-up 4.7k typ tach output v cc figure 9a. fan with tach pull-up to +v cc if the fan output has a resistive pull-up to 12 v (or other voltage greater than 6.5 v), the fan output can be clamped with a zener diode, as shown in figure 9b. the zener voltage should be chosen so that it is greater than v ih but less than 6.5 v, allowing for the voltage tolerance of the zener. a value of between 3 v and 5 v is suitable. 12v fan speed counter tach1 or tach2 tach output zd1 * zener pull-up 4.7k typ * choose zd1 voltage approx. 0.8 v cc v cc figure 9b. fan with tach. pull-up to voltage >6.5 v (e.g., 12 v) clamped with zener diode if the fan has a strong pull-up (less than 1 k ? ) to 12 v, or a totem-pole output, a series resistor can be added to limit the zener current, as shown in figure 9c. alternatively, a resistive attenuator may be used, as shown in figure 9d. r1 and r2 should be chosen such that: 2 v < v pullup r 2/( r pullup + r 1 + r 2) < 5 v the fan inputs have an input resistance of nominally 160 k ? to ground, so this should be taken into account when calculating resistor values. with a pull-up voltage of 12 v and pull-up resistor less than 1 k ? , suitable values for r1 and r2 would be 100 k ? and 47 k ? . this will give a high input voltage of 3.83 v. 12v fan speed counter tach1 or tach2 pull-up typ <1k or totem-pole zd1 zener * r1 10k tach o/p * choose zd1 voltage approx. 0.8 v cc v cc figure 9c. fan with strong tach. pull-up to >v cc or totem-pole output, clamped with zener and resistor 12v fan speed counter tach1 or tach2 tach output r1 * r2 * <1k v cc * see text figure 9d. fan with strong tach. pull-up to >v cc or totem-pole output, attenuated with r1/r2 fan speed control fan s peed is controlled using pulsewidth modulation (pwm). the pwm outp uts (pins 1 and 24) give a pulse output with a programmable frequency (default 250 hz) and a duty-cycle defined by the contents of the relevant fan speed register, or by the automatic fan speed control when this mode is enabled. the speed at which a fan runs is determined by fault conditions and the settings of various control and mask registers. a fan can only be driven if it is defined as being supported by the controller in register 02h. the ADM1029 supports up to two fans, so bits 0 and 1 of this register are permanently set. this register is read-only. rev. 0 ADM1029 C15C a fan will only be driven if it is defined as being supported by the system in register 03h. if bit 0 of this register is set, it indi- cates that fan 1 is installed. this is the power-on default. if bit 1 is set, it indicates that fan 2 is installed. this bit is set by the state of pin 18 at power-up. this register is read/write and the default/power-on setting can be overwritten. if a fan is not supported in register 03h it will not be driven, even if it is physi- cally installed. the pwm outputs are open-drain outputs. they require pull-up resistors and must be amplified and buffered to drive the fans. minimum speed the normal operating fan speed is set by the four lsbs of the fan 1 and fan 2 minimum/alarm speed registers (addresses 60h, 61h). t hese bits also set the minimum speed at which a fan will run in automatic control mode. these bits should be set to 05h. this corresponds to 33% pwm duty-c ycle, which is the lowest speed at which most fans will run reliably. fan(s) will run at minimum speed if there is no fault condition, automatic fan speed is disabled, and there are no other o ver- riding conditions. alarm speed alarm s peed is set by the four msbs of the fan 1 and fan 2 minimum/alarm speed registers (addresses 60h, 61h). fan(s) will run at alarm speed if any of the following conditions occurs, assuming the condition has not been masked out using the fan event mask registers: ? setting bit 0 of register 07h forces fan 1 to run at alarm speed (set fan x alarm speed register). ? setting bit 1 of register 07h forces fan 2 to run at alarm speed (set fan x alarm speed register). if monitoring is disabled by clearing bit 4 of the con- figura tion register, all fans controlled by the ADM1029 will run at alarm speed. ? when a gpio pin is configured as an input by setting bit 0 of the corres ponding gpio behavior register, and bit 4 of the gpio behavior register is also set, all fans controlled by the ADM1029 will go to alarm speed when the logic input is asserted (high or low, depending on the polarity bit, bit 1 of the corresponding gpio behavior register). ? if bit 7 of a fan fault action register is set (18hfan 1, 19h fan 2) the corresponding fan will go to alarm speed when cfault is pulled low by an external source. ? if a tach measurement exceeds the set limit, all fans controlled by the ADM1029 will run at alarm speed. ? if a fan fault input pin is asserted (low), all fans controlled by the ADM1029 will run at alarm speed. ? if bit 1 of a temp. fault action register is set (40hlocal sensor, 41hremote 1, 42hremote 2), all fans controlled by the ADM1029 will go to alarm speed if the corresponding temperature high limit is exceeded. ? if bit 5 of a temp. fault action register is set, all fans con- trolled by the ADM1029 will go to alarm speed if a temperature input crosses the corresponding temperature low limit, the direction depending on the setting of bit 3 of the temp. con- trol register. (0 = alarm when input goes below low limit, 1 = alarm when input goes above low limit). ? if bit 1 of an ain behavior register is set (50hain0, 51hain1), all fans controlled by the ADM1029 will go to alarm speed if the corresponding ain high limit is exceeded. ? if bit 5 of an ain behavior register is set, all fans controlled by the ADM1029 will go to alarm speed if an analog input crosses the corresponding ain low limit, the direction depend- ing on the setting of bit 3 of the ain control register. (0 = alarm when input goes below low limit, 1 = alarm when input goes above low limit). ? if a thermal override occurs while the ADM1029 is in sleep mode, all fans controlled by the ADM1029 will run at alarm speed. hot-plug speed hot-plug speed is set by the four lsbs of the fan 1 and fan 2 configuration registers (addresses 68h and 69h). the pwm frequency is set by bits 4 and 5 of these registers, while bits 6 and 7 set the number of pulses per revolution for fan speed measurement. fan(s) will run at hot-plug speed if any of the following condi- tions occur, assuming the condition has not been masked using the fan event mask registers: ? if a fan is unplugged, the other fan (if any) controlled by the ADM1029 will run at hot-plug speed. ? setting bit 0 of register 08h forces fan 1 to run at hot-plug speed (set fan x hot-plug speed). ? setting bit 1 of register 08h forces fan 2 to run at hot-plug speed (set fan x hot-plug speed). ? when a gpio pin is configured as an input by setting bit 0 of the correspo nding gpio behavior register, and bit 5 of the gpio behavior register is also set, all fans controlled by the ADM1029 will go to hot-plug speed when the logic input is asserted (high or low, depending on the polarity bit, bit 1 of the corresponding gpio behavior register). ? if bit 6 of a fan fault action register is set (18h for fan 1, 19h for fan 2) the corresponding fan will go to hot-plug speed when cfault is pulled low by an external source. note: if operating conditions and register settings are such that both alarm speed and hot-plug speed would be triggered, which one takes priority is determined by bit 5 of the fan 1 and fan 2 status registers (addresses 10h and 11h). if this bit is set, hot-plug speed takes priority. if it is cleared, alarm speed takes priority. full speed fans will run at full speed if the corresponding bits in the set fan x full speed register (address 09h) are set: bit 0 for fan 1 and bit 1 for fan 2. fan mask registers the effect of various conditions on fan speed can be enabled or disabled by mask registers. in all these registers, setting bit 0 of the register enables fan 1 to go to alarm speed or hot-plug speed if the corresponding event occurs, while setting bit 1 enables fan 2. clearing these bits masks the effect of the corresponding event on fan speed. registers 20h and 21h are fan event mask registers. bits 0 and 1 of register 20h enable (bit set) or mask (bit clear) the effect of a fan 1 fault (underspeed or fault input) on fan 1 and fan 2 speed. similarly, bits 0 and 1 of register 21h enable (bit set) rev. 0 ADM1029 C16C or mask (bit clear) the effect of a fan 2 fault on fan 1 and fan 2 speed. registers 38h to 3eh are gpio x event mask registers. bits 0 and 1 of these registers enable or mask the effect of a gpio assertion on fan 1 and fan 2 speed. note: registers 48h to 4ah are temp. cooling action regis- ters. bits 0 and 1 of these registers enable or mask the effect of local, remote 1, and remote 2 temperature faults on fan 1 and fan 2 speed. these registers also determine which tempera- ture channel controls each fan in automatic fan speed control mode, as described later. registers 58h and 59h are ain event mask registers. b its 0 and 1 of these registers enable or mask the effect of an ain out- of-limit event on fan 1 and fan 2 speed. modes of operation the ADM1029 has three different modes of operation. these modes determine the behavior of the system. 1. pwm duty cycle select mode (directly sets fan speed under software control). 2. thermal trip mode 3. automatic fan speed control mode pwm duty cycle select mode the ADM1029 may be operated under software control by clearing bits <1:0> of the three temp cooling action registers (reg 0x48, 0 x49, 0x4a). once under software control, each fan speed may be controlled by programming values of pwm duty cycle in to the device. values of pwm duty cycle between 0% to 100% may be written to the four lsbs of the fan 1 and fan 2 minimum/alarm speed registers (addresses 60h, 61h). to control the speed of each fan. table iv shows the relationship between hex values written to the minimum/alarm speed reg- isters and pwm duty cycle obtained. table iv. pwm duty cycle select mode hex value pwm duty cycle 00 0% 01 7% 02 14% 03 20% 04 27% 05 33% recommended 06 40% 07 47% 08 53% 09 60% 0a 67% 0b 73% 0c 80% 0d 87% 0e 93% 0f 100% (default) it is recommended that the minimum pwm duty cycle be set to 33% (0x05). this has been determined to be the lowest pwm duty cycle that most fans will run reliably at. note that the pwm duty cycle values programmed in to these registers also define the pwm duty cycle that the fans will turn on at, in automatic fan speed control mode. it is recommended that after power- up, the pwm duty cycle is set to 33% before enabling automatic fan speed control. thermal trip mode the ADM1029 can thermally trip the fan(s) for simple on/off fan control, or 2-speed fan control. for example, a fan can be programmed to run at 33% duty cycle. if the temperature exceeds the high temperature limit set for that temperature channel, the fan can automatically trip and run at alarm speed. the fan will continue to run at alarm speed even if the temperature error condition subsides, until the latch temp fault bit (bit 7 of the temp x fault action reg) is cleared in software by writing a 0 to it. to configure fan 1 normally, run at 33% but to thermally trip to alarm speed for a remote 2 measured temperature of 70 c, set up the following registers: 1. configure the normal pwm duty cycle for fan 1 to 33%. fan 1 minimum/alarm speed reg (0 x 60) = 0 xf 5 2. set the remote 2 high temperature limit = 70 c. remote 2 temp high limit reg (0 x 92) = 0 x 46 3. configure alarm speed on overtemperature function for remote 2 temperature channel. set bit 1 of temp 2 fault action reg (0 x 42) 4. enable fan 1 to be controlled by remote 2 temperature. set bit 0 of temp 2 cooling action reg (0 x 4a) once the fan thermally trips to alarm speed, it will continue to run at alarm speed until the temperature drops below the high temperature limit and the latch temp fault bit (bit 7 of the temp 2 fault action reg) is cleared to 0. event latch bits certain events that occur will cause latch bits to be set in vari- ous registers on the ADM1029. once a latch bit is set, it will need to be cleared by software for the system to return to nor- mal operation. to detect if a latch bit has been set, the int pin can be used to signal a latch event to the system supervisor. alternatively, the status registers can be polled periodically, and any latch bits that are set can be cleared. the events that cause latch bits to be set are: 1. thermal events. if the fan is run at alarm speed on over- temperature or undertemperature, this will set the latch temp fault bit (bit 7 of the temp x fault action registers 0x40C0x42). 2. missing fan. if a fan is missing, i.e., has been unplugged, the missing latch bit (bit 1 of fan x status registers) is set. 3. hotplugged fan. if a new fan is inserted into the system, bit 7 (hotplug latch bit) of the fan x status register is set. 4. fault asserted. if the fan becomes stuck and its fault output asserts low, bit 2 (fault latch bit) of the fan x status register is set. 5. tach failure. if the fan runs underspeed or becomes stuck, then bit 6 (tach fault latch bit) of the fan x status regis- ter is set. * bits <3:0> set the minimum pwm duty cycle, bits <7:4> set the alarm speed pwm duty cycle for each fan. rev. 0 ADM1029 C17C automatic fan speed control the ADM1029 has a local temperature channel and two remote tempera ture channels, which may be co nnected to an on-chip diode-connected transistor on a cpu or a general-purpose discrete transistor. these three temperature channels may be used as the basis for an automatic fan speed control loop to drive fans using pulsewidth modulation (pwm). how does the control loop work? the automatic fan speed control loop is shown in figure 10. fan speed max min temperature t min t max = t min + t range spin up for 2 seconds figure 10. automatic fan speed control in order for the fan speed control loop to work, certain loop parameters need to be programmed in to the device: 1. t min . this is the temperature at which a fan should sw itch on and run at minimum speed. the fan will only turn on once the temperature being measured rises above the t min value programmed. the fan will spin up for a predeter- mined time (default = 2 secs). see fan spin-up section for more details. 2. t range . this will be the temperature range over which the ADM1029 will automatically adjust fan speed. as the tempera- ture increases beyond t min , the pwm duty cycle will be increased accordingly. the t range parameter actually defines the fan speed versus temperature slope of the control loop. 3. t max . this is defined as the temperature at which a fan will be at its maximum speed. at this temperature, the pwm duty cycle driving the fan will be 100%. t max is given by t min + t range . since this parameter is the sum of the t min and t range parameters, it does not need to be programmed into a register on-chip. 4. programmable hysteresis is included in the control loop to prevent the fans continuously switching on and off if the temperature is close to t min . the fans will continue to run until such time as the temperature drops below t min Ct hyst . the four msbs of the t range /t hyst registers (registers 0x88, 0 x89, 0x8a) contain a temperature hysteresis value that can be programmed from 0001 to 1111. this allows a temperature hysteresis range from 1 c to 15 c for each temperature measurement channel. pwm duty cycle % 100 53 66 73 87 33 40 47 60 80 93 temperature c t min t max = t min + t range 0 5 10 20 40 80 60 t range = 80 c t range = 40 c t range = 20 c t range = 10 c t range = 5 c figure 11. pwm duty cycle vs. temperature slopes (t range ) figure 11 shows the different control slopes determined by the t range value chosen, and programmed in to the ADM1029. t min was set to 0 c to start all slopes from the same point. it can be seen how changing the t range value affects the pwm duty cycle vs. temperature slope. figure 12 shows how for a given t range , changing the t min value affects the loop. increasing the t min value will increase the t max (temperature at which the fan runs full speed) value, since t max = t min + t range . note, however, that the pwm duty cycle versus temperature slope remains exactly the same. changing the t min value merely shifts the control slope. pwm duty cycle % temperature c t min t max = t min + t range 0 20 40 80 60 t range = 40 c t range = 40 c t range = 40 c 100 53 66 87 40 73 33 47 60 80 93 figure 12. effect of increasing t min value on control loop fan spin-up as previously mentioned, once the temperature being measured exceeds the t min value programmed, the fan will turn on at minimum speed (default = 33% duty cycle). however, the prob- lem with fans being driven by pwm is that 33% duty cycle is not enough to reliably start the fan spinning. the solution is to rev. 0 ADM1029 C18C spin the fan up for a predetermined time, and once the fan has spun up, its running speed may be reduced in line with the temperature being measured. the ADM1029 a llows fan spin-up times between 1/64 second and 16 seconds. the fan spin-up register (register 0x0c) allows the spin-up time for the fans to be programmed. bit 3 of this register, when set, disables fan spin-up for both fans. table v. fan spin-up times spin-up times bits 2:0 (fan spin-up register) 000 16 seconds 001 8 seconds 010 4 seconds 011 2 seconds (default) 100 1 second 101 1/4 second 110 1/16 second 111 1/64 second once the automatic fan speed control loop parameters have been chosen, the ADM1029 device may be programmed. the ADM1029 is placed into automatic fan speed control mode by writing to the three temperature cooling action registers (registers 0x48, 0x49, 0x4a). the device powers up in auto- matic fan speed control mode by default, as long as the t min / install pin (pin 18) does not have the disable option selected (t min /install pin tied low or high). the default setting is that both fans will run at the fastest speed calculated by all three temperature channels. the control mode offers flexibility in that the user can decide which temperature channel/channels control each fan (five options). table vi. automatic mode fan behavior option temperature cooling action 1 bit 0 regis ter 0x49 and/or bit 1 reg 0x4a = remote temp 1 controls fan 1, remote temp 2 controls fan 2 2 bit 0 register 0x48 and bit 1 register 0x48 = 1 local temp controls fan 1 and/or fan 2 3 bit 0 register 0x49 and bit 1 register 0x49 = remote temp 1 controls fan 1 and/or fan 2 4 bit 0 register 0x4a and bit 1 register 0x4a = remote temp 2 controls fan 1 and/or fan 2 5 bits 0, 1 reg 0x48, 0x49, 0x4a = 1 max speed calculated by local and remote temperature channels controls fans 1 and/or 2 when option 5 is chosen, this offers increased flexibility. the local and remote temperature channels can have independently programmed control loops with different control parameters. whichever control loop calculates the fastest fan speed based on the temperature being measured, drives both fans. figure 13 shows how the fans pwm duty cycle is determined by two independent control loops. this is the type of automode fan behavior seen when bits 0 and 1 of all three temperature cooling action registers = 11. figure 13a shows the control loop for the local temperature channel. its t min value has been programmed to 20 c, and its t range value is 40 c. t range = 80 c 02040 7080 remote temperature c t min t max = t min + t range t range = 40 c 100 87 73 66 60 53 47 40 33 93 80 02040 60 local temperature c t min t max = t min + t range pwm duty cycle % pwm duty cycle % 100 87 73 66 60 53 47 40 33 93 80 figure 13. max speed calculated by local and remote temperature control loops drives fans the local temperatures t max will thus be 60 c. figure 13b shows the control loop for the remote 1 temperature channel. its t min value has been set to 0 c, while its t range = 80 c. there- fore, the remote 1 temperatures t max value will be 80 c. if both temperature channels measure 40 c, both control loops will calculate a pwm duty cycle of 66%. therefore, the fans will be driven at 66% duty cycle. if both temperature channels measure 20 c, the local channel will calculate 33% pwm duty cycle, while the remote 1 chan nel will calculate 50% pwm duty cycle. thus, the fans will be driven at 50% pwm duty cycle. consider the local temperature measuring 60 c, while the remote 1 temperature is m easuring 70 c. the pwm duty cycle calculated by the local temperature control loop will be 100% (since the temperature = t max ). the pwm duty cycle calculated by the remote 1 temperature control loop at 70 c will be approximately 90%. so the fans will run full speed (100% duty cycle). remember that the fan speed will be based on the fastest speed calculated, and is not necessarily based on the highest temperature measured. depending on the control loop parameters programmed, a lower temperature on one channel may actually calculate a faster speed than a higher temperature on another channel. a. b. rev. 0 ADM1029 C19C programming the automatic fan speed control loop 1. program a value for t min . 2. program a value for the slope t range . 3. t max = t min + t range . 4. program a value for fan spin-up time. 5. program the desired automatic fan speed control mode behavior, i.e., which temperature channel controls each fan. other control loop parameters? having programmed all the above loop parameters, are there any other parameters to worry about? t min was defined as being the temperature at which a fan switched on and ran at minimum speed. this minimum speed should be set to 33%. if the minimum pwm duty cycle is programmed to 33%, the fan control loops will operate as previ- ously described. it should be noted, however, that changing the minimum pwm duty cycle affects the control loop behavior. 100 33 40 47 53 60 66 73 80 87 93 temperature c t min 0162840 60 pwm duty cycle % t range = 40 c 1 2 3 figure 14. effect of changing minimum duty cycle on control loop with fixed t min and t range values slope 1 of figure 14 shows t min set to 0 c and the t range chosen is 40 c. in this case, the fans pwm duty cycle will vary over the range 33% to 100%. the fan will run full speed at 40 c. if the minimum pwm duty cycle at which the fan runs at t min is changed, its effect can be seen on slopes 2 and 3. take case 2, where the minimum pwm duty cycle is reprogrammed from 33% (default) to 53%. the fan will actually reach full speed at a much lower temperature, 28 c. case 3 shows that when the minimum pwm duty cycle was increased to 73%, the tem- perature at which the fan ran full speed was 16 c. so the effect of increasing the minimum pwm duty cycle, with a fixed t min and fixed t range , is that the fan will actually reach full speed (t max ) at a lower temperature than t min + t range . how can t max be calculated? in automatic fan speed control mode, the registers holding the minimum pwm duty cycle at t min , are the minimum/ alarm speed registers (addresses 60h, 61h). table vii shows the relationship between the decimal values written to the mini- mum/alarm speed registers and pwm duty cycle obtained. table vii. programming pwm duty cycle decimal value pwm duty cycle 00 0% 01 7% 02 14% 03 20% 04 27% 05 33% recommended 06 40% 07 47% 08 53% 09 60% 10 (0x0a) 67% 11 (0x0b) 73% 12 (0x0c) 80% 13 (0x0d) 87% 14 (0x0e) 93% 15 (0x0f) 100% (default) * bits <3:0> set the minimum pwm duty cycle for automatic mode. bits <7:4> set the alarm speed pwm duty cycle. the temperature at which each fan will run full speed (100% duty cycle) is given by: t max = t min + (( max dc C min dc ) t range /10) where, t max = temperature at which fan runs full speed t min = temperature at which fan will turn on max dc = maximum duty cycle (100%) = 15 decimal min dc = duty cycle at t min , programmed into fan speed config register (default = 33% = 5 decimal) t range = pwm duty cycle versus temperature slope example 1 t min =0 c, t range = 40 c min dc = 53% = 8 decimal (table vii) calculate t max t max =t min + (( max dcCmin dc) t range /10) t max = 0 + ((100% dc C 53% dc) 40/10) t max = 0 + ((15 C 8) 4) = 28 t max = 28 c. (as seen on slope 2 of figure 14) example 2 t min =0 c, t range = 40 c min dc = 73% = 11 decimal (table vii) calculate t max t max = t min + ((max dcCmin dc) t range /10) t max = 0 + ((100% dc C 73% dc) 40/10) t max = 0 + ((15 C 11) 4) = 16 t max = 16 c. (as seen on slope 3 of figure 14) example 3 t min = 0 c, t range = 40 c min dc = 33% = 5 decimal from table iv calculate t max t max = t min + ((max dcCmin dc) t range /10) t max = 0 + ((100% dc C 33% dc) 40/10) t max = 0 + ((15 C 5) 4) = 40 t max = 40 c. (as seen on slope 1 of figure 14) rev. 0 ADM1029 C20C measure fan speed fan 1 (reg 0x70) fan 2 (reg 0x71) program fan minimum duty cycle fan 1 (reg 0x60) fan 2 (reg 0x61) configure temp cooling action local temp (reg 0x48) remote 1 temp (reg 0x49) remote 2 temp (reg 0x4a) program fan start temperature, t min local temp (reg 0x80) remote 1 temp (reg 0x81) remote 2 temp (reg 0x82) program temp-to-fan speed control slope, t range local temp (reg 0x88) remote 1 temp (reg 0x89) remote 2 temp (reg 0x8a) configure control loop hysteresis local temp (reg 0x88) remote 1 temp (reg 0x89) remote 2 temp (reg 0x8a) configure fan spin-up time (register 0x0c) configure pwm drive frequency fan 1 (reg 0x68) fan 2 (reg 0x69) configure tach oscillator frequency fan 1 (reg 0x68) fan 2 (reg 0x69) temp cooling action (configure reg 0x48 for local temp, reg 0x49 for remote 1 temp and reg 0x4a for remote 2 temp) option 1 option 2 option 3 option 4 option 5 ADM1029 remote 1 temperature remote 2 temperature fan 1 fan 2 option 1 ADM1029 local temp fan 1 fan 2 option 2 ADM1029 remote 1 temperature fan 1 fan 2 option 3 remote 2 temperature remote 2 temperature ADM1029 remote 1 temperature fan 1 fan 2 option 4 remote 1 temperature remote 2 temperature fan 1 fan 2 option 5 ADM1029 local temp bit 0 (reg 0x49) and/or bit 1 (reg 0x4a) = 1 remote 1 temp controls fan 1 remote 2 temp controls fan 2 bit 0 (reg 0x48) and bit 1 (reg 0x48) = 1 local temp controls fan 1 and/or fan 2 bit 0 (reg 0x49) and bit 1 (reg 0x49) = 1 remote 1 temp controls fan 1 and/or fan 2 bit 0, 1 (reg 0x48, 0x49, 0x4a) = 1 fan 1 and/or fan 2 runs at fastest speed calculated by all temperature channels bit 0 (reg 0x4a) and bit 1 (reg 0x4a) = 1 remote 2 temp controls fan 1 and/or fan 2 figure 15. configuring automatic fan speed control rev. 0 ADM1029 C21C fan-related registers table ix is a list of registers on the ADM1029 that are specific to fan speed measurement and control: table ix. fan-specific registers address description 0x02 fans supported by controller 0x03 fans supported in system 0x07 set fan x alarm speed 0x08 set fan x hot-plug speed 0x09 set fan x full speed 0x10 fan 1 status 0x11 fan 2 status 0x18 fan 1 fault action 0x19 fan 2 fault action 0x20 fan 1 event mask 0x21 fan 2 event mask 0x48 local temp cooling action 0x49 remote 1 cooling action 0x4a remote 2 cooling action 0x60 fan 1 minimum/alarm speed 0x61 fan 2 minimum/alarm speed 0x68 fan 1 configuration 0x69 fan 2 configuration 0x70 fan 1 tach value 0x71 fan 2 tach value 0x78 fan 1 tach high limit 0x79 fan 2 tach high limit fan configuration registers registers 0x68 and 0x69 are the fan 1 and fan 2 configuration registers. these allow the pwm output frequencies to be selected for each fan. the default pwm drive frequency is 250 hz. bits <7:6> adjust the fan tach oscillator frequency for fan tach mea- surements. bits <3:0> allow the hot plug pwm duty cycle value for each fan to be programmed. figures 16 and 17 show how to configure the fans to handle thermal or fault events. table viii. resistor ratios for setting t min and number of fans installed using tmin/install pin (pin 18) 3 msbs ideal ratio r1 r2 actual error fans of adc r2/(r1 + r2) (k )(k ) r2/(r1 + r2) (%) t min installed 111 n/a 0 1 0 disabled 2 110 0.8125 18 82 0.82 0.75 48 c2 101 0.6875 22 47 0.6812 C0.63 40 c2 100 0.5625 12 15 0.5556 C0.69 32 c2 011 0.4375 15 12 0.4444 0.69 32 c1 010 0.3125 47 22 0.3188 0.63 40 c1 001 0.1875 82 18 0.18 C0.75 48 c1 000 n/a 0 0 0 disabled 1 in this case, since the minimum duty cycle is the default 33%, the equation for t max reduces to: t max = t min + ((max dc C min dc) t range /10) t max = t min + ((15 C 5) t range /10) t max = t min + (10 t range /10) t max = t min + t range enabling automatic fan speed control using tmin/install pin (pin 18) automatic fan control can also be enabled in hardware by pin 18 (tmin/install). this is an 8-level input with multiple functions, which is sampled only at power-up. if only one fan is installed, the voltage on pin 18 should be kept at less than v cc /2, which clears bit 1 of register 03h. within this voltage range, four voltage levels define the minimum temperature at which the fan will operate in automatic speed control mode. if two fans are installed, the voltage on pin 18 should be between v cc /2 and v cc , which sets bit 1 of register 03h. within this voltage range, four voltage levels define the minimum temperature at which the fans will operate in automatic speed control mode. resistor values for setting the voltage on pin 18 are given in table viii. if automatic fan speed control is not used, pin 18 can simply be strapped to ground (one fan) or v cc (two fans), depending on how many fans are installed. under this condi- tion, the fans will run full s peed until the device is written to by software to change fan speed. when automatic fan speed control is enabled at power-up by the tmin/install pin, bit 4 of the configuration register is set to enable monitoring, and bits 0 and 1 of all temp. cooling action registers are set, so any temperature channel will auto- matically control all fans that are installed. note: if automatic fan speed control is enabled and an event occurs that would cause a fan to go to alarm or hot-plug speed (e.g., temperature fault), that event will override the automatic fan speed control. if the event affects only one fan, the other fan will remain under automatic control. rev. 0 ADM1029 C22C bit 0 = 1 assert cfault on fan fault (tach failure or fault assertion) bit 1 = 1 assert int on fan fault (tach failure or fault assertion) bit 2 = 1 assert cfault if fan hot unplugged bit 3 = 1 assert int if fan hot unplugged bit 4 = 1 thermal override if in sleep mode (fan runs at alarm speed) bit 5 = 1 drive fault low if a fan fault is detected bit 6 = 1 if cfault pulled low externally, run fan at hot-plug speed bit 7 = 1 if cfault pulled low externally, run fan at alarm speed 7 6 5 4 3 2 1 0 configure fan fault mask registers fan 1 (reg 0x20) fan 2 (reg 0x21) configure fan alarm speed fan 1 (reg 0x60) fan 2 (reg 0x61) defaults fan 1 = 100% fan 2 = 100% configure fan normal speed fan 1 (reg 0x60) fan 2 (reg 0x61) set fan 1 = 33% set fan 2 = 33% configure fan hot-plug speed fan 1 (reg 0x68) fan 2 (reg 0x69) fan tach failure or fault pin low? cfault yes yes fan runs at alarm speed has a fan been hot unplugged? yes int over- temperature detected in sleep mode? yes yes fan runs at alarm speed has cfault been pulled low? yes configure fan fault action fan 1 (reg 0x18) fan 2 (reg 0x19) fan tach failure or fault pin low? cfault has a fan been hot unplugged? yes int fan tach failure or fault pin low? fan runs at hot-plug speed yes fan fault action (configure reg 0x18 for fan 1, reg 0x19 for fan 2) bits 2 7 don't care fan fault mask (configure reg 0x20 for fan 1, reg 0x21 for fan 2) fan tach failure or fault pin low? fan tach failure or fault pin low? fan 1 runs alarm speed fan 2 runs alarm speed yes yes defaults fan 1 = 100% fan 2 = 100% has cfault been pulled low? bit 0 = 1 run fan 1 at alarm speed if fan fault is detected bit 1 = 1 run fan 2 at alarm speed if fan fault is detected figure 16. fan configuration flowchart rev. 0 ADM1029 C23C measure fan speed fan1 (reg 0x70) fan2 (reg 0x71) configure gpio event mask registers (reg 0x38 0x3e) configure temp cooling action local temp (reg 0x48) remote 1 temp (reg 0x49) remote 2 temp (reg 0x4a) configure ain event mask registers ain1 (reg 0x58) ain2 (reg 0x59) is gpio pin asserted? yes yes fan runs at alarm or hot-plug speed gpio event mask (configure reg 0x38 for gpio0, reg 0x39 for gpio1.....reg 0x3e for gpio6) bit 0 = 1 fan 1 runs at alarm or hot-plug speed if gpio pin is asserted bit 1 = 1 fan 2 runs at alarm or hot-plug speed if gpio pin is asserted bits 2 7 don't care program fan start temperature, t min local temp (reg 0x80) remote 1 temp (reg 0x81) remote 2 temp (reg 0x82) program temp-to-fan speed control slope, t range local temp (reg 0x88) remote 1 temp (reg 0x89) remote 2 temp (reg 0x8a) configure control loop hysteresis local temp (reg 0x88) remote 1 temp (reg 0x89) remote 2 temp (reg 0x8a) ain event mask (configure reg 0x58 for ain 0, reg 0x59 for ain 1) bit 0 = 1 fan 1 runs at alarm speed if ain out-of-limit event occurs bit 1 = 1 fan 2 runs at alarm speed if ain out-of-limit event occurs is ain pin asserted? fan runs at alarm speed automatic fan speed control configuration (refer to automatic fan speed control flowchart) configure fan spin-up time register 0x0c configure pwm drive frequency fan1 (reg 0x68) fan2 (reg 0x69) configure tach oscillator frequency fan1 (reg 0x68) fan2 (reg 0x69) bits 2 7 don't care figure 17. fan configuration flowchart (continued) rev. 0 ADM1029 C24C reset input pin 12 is an active-low system reset input. taking this pin low will generate a system reset, which will reset all registers to their default values. analog inputs pins 19 and 20 of the ADM1029 are dual-function pins. they may be configured as general-purpose logic i/o pins by setting bits 0, 1 of the gpio present/ain register (address 05h) or as 0 v to 2.5 v analog inputs by clearing these bits. in the analog input mode, pins 19 and 20 have an input range of 0 v to 2.5 v. by suitable input scaling, the analog input may be configured to measure other voltage ranges such as system power s upply voltages. if more than one ADM1029 is used in a system, several such voltages may be monitored. the measured values of ain0 and ain 1 are stored in the ain0 and ain1 value registers (addresses b8h and b9h) and are compared to high and low limits stored in the ain0 and ain1 high and low limit registers (addresses a8h, a9h and b0h, b1h). the response of the ADM1029 to an out-of-limit measurement on ain0 or ain1 depends on the status of the ain0 and ain1 behavior registers (registers 50h, 51h). the response of cfault , int , and fan speed to temperature events depends on the setting of these registers, as detailed in the register tables later in this data sheet. figure 18 shows how the ain pins can be configured to respond to different events. analog monitoring cycle the ADM1029 performs a sequential round-robin, monitor- ing cycle on all analog inputs and temperature inputs that are enabled. a conversion on ain0 or ain1 typically takes 11.6 ms, while an external temperature conversion takes 185.6 ms. interrupt (int ) output the int output is an open-drain output with selectable polar- ity, intended to communicate fault conditions to the host processor. the polarity is set to active low by clearing bit 7 of the configuration register (address 01h) or to active high by setting this bit. int can be asserted if any of the following conditions occur: ? a hot-plug event. ? setting bit 6 of the configuration register (address 01h) forces int to be asserted. ? when a gpio pin is configured as an input by setting bit 0 of the corresponding gpio behavior register and bit 3 of the gpio behavior register is also set, int will be asserted when the logic input is asserted (high or low, depending on the polar- ity bit, bit 1 of the corresponding gpio behavior register). ? if bit 2 of a temp. fault action register is set (40hlocal sensor, 41hremote 1, 42hremote 2), int will be asserted if the corresponding temperature high limit is exceeded. ? if bit 6 of a temp. fault action register is set, int will be asserted if a temperature input crosses the corresponding temperature low limit, the direction depending on the setting of bit 3 of the temp. fault action register. (0 = int when temperature goes below low limit, 1 = int when temperature goes above low limit). ? if bit 1 of a fan fault action register (18h or 19h) is set, int will be asserted when a tach measurement for the corre- sponding fan exceeds the set limit . ? if bit 1 of a fan fault action register (18h or 19h) is set, int will be asserted when the fan fault input pin for the cor- responding fan is asserted (low). ? if bit 2 of an ain behavior register is set (50hain0, 51h ain1), int will be asserted if the corresponding ain high limit is exceeded. ? if bit 6 of an ain behavior register is set, int will be asserted if the corresponding analog input crosses its ain low limit, the direction depending on the setting of bit 3 of the ain behavior register. (0 = int when input goes below low limit, 1 = int when input goes above low limit). fan free-wheeling test the fan free wheeling test is used to diagnose fans connected to the ADM1029 to ensure that they are operating correctly. large fans tightly coupled in a duct can affect each others air- flow. if one fan has failed it may not be apparent, as the other fan moving can suck air through the faulty fan causing it to spin. the ADM1029 will spin each fan up separately with the other powered down and measure the fan speed of both. when it tries to spin the failed fan with the working fan off, the fan speed measurement will fail, and the faulty fan will be detected. the fan free-wheel test can be invoked at any time in software by setting bit 3 of the configuration register (reg. 0x01). the fan free-wheel test normally takes about 10 seconds. once the fan free-wheel test has completed, bit 3 will automatically clear to 0. automatic fan free-wheel test whenever a fan is hot-plugged, the fan free-wheel test is automatically invoked. bit 3 gets set high automatically and once the test has completed, self-clears to 0. if 2 fans are installed in the system, the fan free-wheel test is invoked by removing the suspect fan and hotplugging a new one. when the suspect fan (e.g., fan 1) is removed, the missing bit (bit 0) and missing latch bit (bit 1) of the fan 1 status register are set. fan 2 will then automatically run at hotplug speed. if the fau lty fan is replaced, the hotplug latch bit (bit 7) is set and the missing bit (bit 0) self-clears. (however, the missing latch bit remains set.) fan 2 will return to its previous value automatically and the fan free-wheel test is invoked. fan 1 is run at 100% while fan 2 is turned off. fan 2 is then run at 100% with fan 1 turned off. both fans are then spun-up for the fan spin-up time. note that the hotplug latch bit and missing latch bit remains set (bits 7 and 1). these need to be cleared to 0 before a subse- quent fan free-wheel test can occur. otherwise, subsequent fan removals and insertions are ignored. rev. 0 ADM1029 C25C bit 0 = 1 cfault asserted if ain value exceeds ain high limit bit 1 = 1 fans run alarm speed if ain value exceeds ain high limit bit 2 = 1 int asserted if ain value exceeds ain high limit bit 3 = 0 alarm generated ( int , cfault , or alarm speed) when ain goes below ain low limit bit 3 = 1 alarm generated ( int , cfault , or alarm speed) when ain goes above ain low limit bit 4 = 1 cfault asserted if ain value exceeds ain low limit. bit 3 decides whether cfault is asserted going above or below the low limit bit 5 = 1 fans run alarm speed if ain value crosses the ain low limit. bit 3 decide whether alarm speed is triggered going above or below the low limit bit 6 = 1 int asserted if ain value crosses the ain low limit. bit 3 decides whether int is asserted going above or below the low limit bit 7 = 1 this bit latches an out-of-limit ain event. cleared by writing a '0' 7 6 5 4 3 2 1 0 ain pins behavior (reg 0x50 configures ain0, reg 0x51 configures ain1) bit 0 = 0 pin 19 configured as ain0 bit 1 = 0 pin 20 configured as ain1 bit 2 7 reserved for other functions ain pins enable (reg 0x05) enable pins for ain function (register 0x05) configure ain pins behavior ain0 (reg 0x50) ain1 (reg 0x51) configure ain event mask ain0 (reg 0x58) ain1 (reg 0x59) bit 0 = 1 run fan 1 at alarm speed if ain out-of- limit event is detected bit 1 = 1 run fan 2 at alarm speed if ain out-of- limit event is detected bits 2 7 reserved read back zero ain event mask (configure reg 0x58 for ain0, reg 0x59 for ain1) is ain value > ain high limit? cfault yes yes fans run alarm speed yes int ain above or below low ain limit? 0 = alarm below ain low limit 1 = alarm above ain low limit has ain value exceeded ain low limit? cfault yes yes fans run alarm speed yes int is ain value > ain high limit? is ain value > ain high limit? has ain value exceeded ain low limit? has ain value exceeded ain low limit? configure ain high limits ain0 (reg 0xa8) ain1 (reg 0xa9) configure ain low limits ain0 (reg 0xb0) ain1 (reg 0xb1) measure ain voltages ain0 (reg 0xb8) ain1 (reg 0xb9) figure 18. configuring ain0 and ain1 pins rev. 0 ADM1029 C26C general purpose logic input/outputs the ADM1029 has six dual-function pins (see pin function descriptions section) that may be configured as general-purpose logic i/o pins by setting the appropriate bit(s) of the gpio present/ain register (address 05h) or as their alternate func- tions by clearing these bits. when configured as gpio pins, each gpio pin has a behavior register associated with it (registers 28h to 2eh) that may be used to configure the operation of the pin. the gpio pins may be configured as inputs or outputs. when used as inputs, they may be configured to: ? be active high or active low. ? set/clear a bit in the behavior register when gp input is asserted/deasserted. ? latch a bit in the behavior register when gp input is asserted (must be cleared by software). ? assert cfault when gp input asserted. ? assert int when gp input asserted. ? set fan(s) to alarm speed when gp input asserted. ? set fan(s) to hot-plug speed when gp input asserted. when used as outputs, they may be configured to: ? be active high or low ? be asserted if a high temperature limit is exceeded. ? be asserted if a temperature measurement falls below a low limit. ? be asserted if a fan fault is detected. ? be asserted if a fan tach limit is exceeded. ? be asserted if an ain high limit is exceeded. ? be asserted if an analog input falls below a low limit. figure 19 shows how to configure the gpio pins to handle different out-of-limit and fault events. cfault output the cascade fault output ( cfault ), is an open-drain, active low output, intended to communicate fault conditions to other ADM1029s in a system, without the intervention of the host pro- cess or. the other ADM1029s may then adjust their fans speed to compensate, depending on the settings of various registers. cfault is asserted if any of the following conditions occurs: ? a hot-plug event. ? setting bit 5 of the configuration register (address 01h) forces cfault to be asserted. ? when a gpio pin is configured as an input by setting bit 0 of the c orresponding gpio behavior register and bit 2 of the gpio behavior register is also set, cfault will be asserted when the logic input is asserted (high or low depending on the polarity bit, bit 1 of the corresponding gpio behavior register). ? if bit 0 of a temp. fault action register is set (40hlocal sensor, 41hremote 1, 42hremote 2), cfault will be asserted if the corresponding temperature high limit is exceeded. ? if bit 4 of a temp. fault action register is set, cfault will be asserted if a temperature input crosses the corresponding temperature low limit, the direction depending on the setting of bit 3 of the temp. fault action register. (0 = cfault when input goes below low limit, 1 = cfault when input goes above low limit). ? if bit 0 of a fan fault action register (18h or 19h) is set, cfault will be asserted when a tach measurement for the corresponding fan exceeds the set limit. ? if bit 0 of a fan fault action register (18h or 19h) is set, cfault will be asserted, when the fan fault input pin for the corresponding fan is asserted (low). ? if bit 0 of an ain behavior register is set (50hain0, 51hain1), cfault will be asserted if the corresponding ain high limit is exceeded. ? if bit 4 of an ain behavior register is set, cfault will be asserted if an analog input crosses the corresponding ain low limit, the direction depending on the setting of bit 3 of the ain behavior register. (0 = cfault when input goes below low limit, 1 = cfault when input goes above low limit). rev. 0 ADM1029 C27C bit 0 = 1 run fan 1 at alarm or hot-plug speed if gpio pin is asserted bit 1 = 1 run fan 2 at alarm or hot-plug speed if gpio pin is asserted bits 2 7 reserved read back zero bit 0 = 1 pin 19 configured as gpio0 bit 1 = 1 pin 20 configured as gpio1 bit 2 = 1 pin 11 configured as gpio2 bit 3 = 1 pin 13 configured as gpio3 bit 4 = 1 pin 14 configured as gpio4 bit 5 = 1 pin 16 configured as gpio5 bit 6 = 1 pin 17 configured as gpio6 bit 7 reserved enable pins for gpio function (register 0x05) configure gpio pins behavior gpio0 (reg 0x28) | gpio6 (reg 0x2e) configure gpio event mask gpio0 (reg 0x38) | gpio6 (reg 0x3e) fan 1 runs at hot-plug or alarm speed gpio pins enable (reg 0x05) gpio event mask (configure reg 0x38 for gpio0, reg 0x39 for gpio1.....reg 0x3e for gpio6) is gpio pin asserted? yes bit 0 sets the direction for gpio pin. a '0' configures the pin as an output, a '1' sets the pin up as an input bit 1 sets the polarity for gpio pin. a '0' makes the pin active low, a '1' makes the pin active high bit 2 = 1 if gpio pin is configured as an input, cfault is asserted when gpio is asserted. if gpio pin is configured as an output, gpio pin will be asserted if a high temperature limit is exceeded. this can be used to shut down the system in an over-temperature situation. bit 3 = 1 if gpio pin is configured as an input, int is asserted when gpio is asserted. if gpio pin is an output, gpio is asserted if a temperature low limit is exceeded. bit 4 = 1 if gpio pin is configured as an input, fans go to alarm speed if gpio is asserted. if gpio pin is an output, gpio is asserted if a fan tach limit is exceeded. bit 5 = 1 if gpio pin is configured as an input, fans go to hot-plug speed if gpio is asserted. if gpio pin is an output, gpio is asserted if a fan fault is detected (fault pin). bit 6 = 1 if gpio pin is an input, this bit reflects the state of gpio pin. if gpio pin is an output, gpio is asserted if an ain high limit is exceeded. bit 7 if gpio pin is an input, this bit latches a gpio assertion event. cleared by writing a '0.' if gpio pin is an input, gpio is asserted if an ain low limit is exceeded. gpio pins behavior (reg 0x28 configures gpio0, reg 0x29 configures gpio1, etc.) is gpio pin asserted? yes fan 2 runs at hot-plug or alarm speed & '4 . b-;- rev. 0 ADM1029 C28C table x. register map address name default value description 00 status register 00h contains the status of various fault conditions. 01 config register 0000 0000 configures the operation of the device. 02 fan supported by controller 03h contains the number of fans the device can support. 03 fans supported in system 0000 00?1 contains the number of fans actually supported by the device in the application. 04 gpios supported by controller 7fh contains the number of gpio pins the device can support. 05 gpio present/ain 0????111 used to configure gpio pins as gpio or as their alternate analog input function. 06 temp devices installed 0000 0??1 contains number of temperature sensors installed. 07 set fan x alarm speed 00h writing to appropriate bit(s) makes fan(s) run at alarm speed. 08 set fan x hot-plug speed 00h wr iting to appropriate bit(s) makes fan(s) run at hot-plug speed. 09 set fan x full speed 00h writing to appropriate bit(s) makes fan(s) run at full speed. 0b s/w reset 00h writing a6h to this register causes a software reset. 0c fan spin-up 03h configures fan spin-up time. 0d manufacturers id 41h this register contains the manufacturers id code for the device. 0e major/minor revision 00h contains the manufacturers code for major and minor revi- sions to the device in two nibbles. 0f manufacturers test register 00h this register is used by the manufacturer for test purposes. it should not be read from or written to in normal operation. 10 fan 1 status 0000 0?0? contains status information for fan 1. 11 fan 2 status 0000 0?0? contains status information for fan 2. 18 fan 1 fault action bfh sets operation of int , cfault , etc., for fan 1 fault. 19 fan 2 fault action bfh sets operation of int , cfault , etc., for fan 2 fault. 20 fan 1 event mask ffh enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to a fault or hot-plug event on fan 1. 21 fan 2 event mask ffh enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to a fault or hot-plug event on fan 2. 28 gpio0 behavior 00h configures the operation of gpio0. 29 gpio1 behavior 00h configures the operation of gpio1. 2a gpio2 behavior 00h configures the operation of gpio2. 2b gpio3 behavior 00h configures the operation of gpio3. 2c gpio4 behavior 00h configures the operation of gpio4. 2d gpio5 behavior 00h configures the operation of gpio5. 2e gpio6 behavior 00h configures the operation of gpio6. 30 local temperature offset 00h offset register for local temperature measurement. the value in this register is added to the local temperature v alue to reduce system offset effects. 31 remote 1 temperature offset 00h offset register for first remote temperature channel (d1). the value in this register is added to the temperature value to reduce system offset effects. 32 remote 2 temperature offset 00h offset register for second remote temperature channel (d2). the value in this register is added to the temperature value to reduce system offset effects. 38 gpio0 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to gpio0 being asserted. 39 gpio1 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to gpio1 being asserted. 3a gpio2 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to gpio2 being asserted. 3b gpio3 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to gpio3 being asserted. rev. 0 ADM1029 C29C table x. register map (continued) address name default value description 3c gpio4 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to gpio4 being asserted. 3d gpio5 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to gpio5 being asserted. 3e gpio6 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to gpio6 being asserted. 40 local temp fault action 08h configures the operation of int , cfault , etc. for a local temp fault (internal temperature sensor). 41 remote 1 temp fault action 08h configures the operation of int , cfault , etc. for a remote 1 temp fault (d1 temperature sensor). 42 remote 2 temp fault action 08h configures the operation of int , cfault , etc. for a remote 2 temp fault (d2 temperature sensor). 48 local temp cooling action 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to a local temp event (internal temperature sensor). 49 remote 1 temp cooling action 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to a remote 1 temp event (d1 temperature sensor). 4a remote 2 temp cooling action 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to a remote 2 temp event (d2 temperature sensor). 50 ain0 behavior 00h configures the operation of int , cfault , etc. for a fault on analog channel 0. 51 ain1 behavior 00h configures the operation of int , cfault , etc. for a fault on analog channel 1. 58 ain0 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to a fault on channel 0. 59 ain1 event mask 00h enables/disables fan 1 and/or fan 2 alarm/hot-plug speed in response to a fault on channel 1. 60 fan 1 minimum/alarm speed ffh contains the minimum/alarm speeds for fan 1. 61 fan 2 minimum/alarm speed ffh contains the minimum/alarm speeds for fan 2. 68 fan 1 configuration 2fh configures hot-plug speed, pwm and tach frequency. 69 fan 2 configuration 2fh configures hot-plug speed, pwm and tach frequency. 70 fan 1 tach value 00h contains the measured value from the fan 1 tachometer o utput. 71 fan 2 tach value 00h contains the measured value from the fan 2 tachometer o utput. 78 fan 1 tach high limit ffh contains the high limit for fan 1 tachometer measurement. 79 fan 2 tach high limit ffh contains the high limit for fan 2 tachometer measurement. 80 local temp t min ??h defines the starting temperature for the fan when controlled by the local temperature channel, under automatic fan speed control. 81 remote 1 temp t min ??h defines the starting temperature for the fan when controlled by the remote 1 temperature channel, under automatic fan speed control. (d1 temp sensor). 82 remote 2 temp t min ??h defines the starting temperature for the fan when controlled by the remote 2 temperature channel, under automatic fan speed control. (d2 temp sensor). 88 local temp t range /t hyst 51h this register programs the control range for the local tempera- ture control loop. it also defines the amount of temperature hysteresis applied to the loop. 89 remote 1 temp t range /t hyst 51h this register programs the control range for the remote 1 temperature control loop. it also defines the amount of tem- perature hysteresis applied to the loop. rev. 0 ADM1029 C30C table x. register map (continued) address name default value description 8a remote 2 temp t range /t hyst 51h this register programs the control range for the remote 2 temperature control loop. it also defines the amount of tem- perature hysteresis applied to the loop. 90 local temp high limit 50h (80 c) high limit for local measurement (internal sensor). 91 remote 1 temp high limit 64h (100 c) high limit for remote 1 measurement (d1 sensor). 92 remote 2 temp high limit 64h (100 c) high limit for remote 2 measurement (d2 sensor). 98 local temp low limit 3ch (60 c) low limit for local temp measurement (internal sensor). 99 remote 1 temp low limit 46h (70 c) low limit for remote 1 measurement (d1 sensor). 9a remote 2 temp low limit 46h (70 c) low limit for remote 2 measurement (d2 sensor). a0 local temp value 00h measured value from local temp sensor. a1 remote 1 temp value 00h measured value from d1 remote sensor. a2 remote 2 temp value 00h measured value from d2 remote sensor. a8 ain0 high limit ffh high limit for measurement on analog channel 0. a9 ain1 high limit ffh high limit for measurement on analog channel 1. b0 ain0 low limit 00h low limit for measurement on analog channel 0. b1 ain1 low limit 00h low limit for measurement on analog channel 1. b8 ain0 measured value 00h measured value of analog channel 0. b9 ain1 measured value 00h measured value of analog channel 1. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C31C configuration registers register 01h ?config register (power-on default 000? 000?) bit name r/w description 0 install = ? r/w this bit reflects bit 1 of register 0x03 (fans supported in system). 1 global int mask = 0 r/w setting this bit to 1 will disable the int output for all interrupt sources. 2 ara disable = 0 r/w setting this bit to 1 will disable the smbus alert response address feature. 3 perform free-wheel r/w setting this bit to 1 will initiate the fan free-wheeling test. while this test test = 0 is being performed normal monitoring of fan speeds, temperature and volt- ages will be temporarily halted. this bit will automatically reset to 0 once the test is complete which will take about 10 seconds. 4 start monitoring = 0 r/w set to 1 to start round robin monitoring cycle of voltage temperature and fan speeds, fault detection, etc. while this bit is 0, all fans will run at alarm speed. this bit is set at power-up; otherwise, if automatic fan speed control is enabled by pin 18. 5 force cfault = 0 r/w setting this bit to 1 forces cfault to be asserted (low). 6 force int = 0 r/w setting this bit to 1 forces int to be asserted (polarity depends on bit 7). 7 int polarity = 0 r/w polarity of int when asserted. 1 means high and 0 means low. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. register 05h ?gpio present / ain (power-on default 0????111) bit name r/w description 0 gpio 0 = 1 r/w indicates that gpio0 is being used. set to 1 on power-up, but can be over- written by software. setting this bit to 0 means ain0 is being used. 1 gpio 1 = 1 r/w indicates that gpio1 is being used. set to 1 on power-up, but can be over- written by software. setting this bit to 0 means ain1 is being used. 2 gpio 2 = 1 r/w indicates that gpio2 is being used. set to 1 on power-up, but can be over- written by software. 3 gpio 3 = ? r/w indicates that gpio3 is being used. setting this bit to 0 means tdm1 is being used. the ADM1029 can detect on power-up if tdm1 is connected. if so, this bit is set to 0, otherwise it is set to 1. the default setting can be overwritten by software. 4 gpio 4 = ? r/w indicates that gpio4 is being used. setting this bit to 0 means tdm1 is being used. the ADM1029 can detect on power-up if tdm1 is connected. if so, this bit is set to 0, otherwise it is set to 1. the default setting can be overwritten by software. 5 gpio 5 = ? r/w indicates that gpio5 is being used. setting this bit to 0 means tdm2 is being used. the ADM1029 can detect on power-up if tdm2 is connected. if so, this bit is set to 0, otherwise it is set to 1. the default setting can be overwritten by software. 6 gpio 6 = ? r/w indicates that gpio6 is being used. setting this bit to 0 means tdm2 is being used. the ADM1029 can detect on power-up if tdm2 is connected. if so, this bit is set to 0, otherwise it is set to 1. the default setting can be overwritten by software. 7 reserved r unused. will read back 0. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C32C register 07h ?set fan x * alarm speed (power-on default 00h) bit name r/w description 0 fan 1 alarm speed = 0 r/w when set to 1, fan 1 will run at alarm speed. 1 fan 2 alarm speed = 0 r/w when set to 1, fan 2 will run at alarm speed. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. notes * x denotes the fan number. question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. register 08h ?set fan x * hot-plug speed (power-on default 00h) bit name r/w description 0 fan 1 hot-plug speed = 0 r/w w hen set to 1, fan 1 will run at hot-plug speed. 1 fan 2 hot-plug speed = 0 r/w w hen set to 1, fan 2 will run at hot-plug speed. 2 0 r unused. will read back 0. 3 0 r unused. will read back 0. 4 0 r unused. will read back 0. 5 0 r unused. will read back 0. 6 0 r unused. will read back 0. 7 0 r unused. will read back 0. notes * x denotes the fan number. question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. register 09h ?set fan x * full speed (power-on default 00h) bit name r/w description 0 fan 1 full speed = 0 r/w when set to 1 fan 1 will run at full speed. 1 fan 2 full speed = 0 r/w when set to 1 fan 2 will run at full speed. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. notes * x denotes the fan number. question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C33C status registers register 00h ?status register (power-on default 00h) bit name r/w description 0 int r this bit is set to 1 when the device is asserting int low. this bit is the logical or of several bits in other registers and is cleared when these bits are cleared. 1 cfault_in r t his bit is set to 1 when the device is receiving cfault low from another device. 2 cfault_out r t his bit is set to 1 when the device is asserting cfault low. this bit is the logical or of several bits in other registers and is cleared when these bits are cleared. 3 in alarm_speed r this bit is set to 1 when either fan is running at alarm speed. this bit is the logical or of several bits in other registers and is cleared when these bits are cleared. 4 in hot-plug speed r this bit is set to 1 when either fan is running at hot-plug speed. this bit is the logical or of several bits in other registers and is cleared when these bits are cleared. 5 gpio/ain event r this bit is a logical or of bits 1, 3, 6, and 7 in the gpio behavior registers at 28h to 2eh while they are configured as inputs, and bit 7 in the ain behavior registers at 50h and 51h. it will be set when any of these bits are set and cleared when all of these bits are cleared. 6 hot plug/fan fault r this bit is a logical or of bits 1, 3, 6, and 7 in the fan status registers at 10h and 11h. it will be set when any of these bits are set and cleared when all of these bits are cleared. 7 thermal event r this bit is a logical or of bit 7 in the temp fault action registers at 40h, 41h, and 42h. it will be set when any of these bits are set and cleared when all of these bits are cleared. register 02h ?fan supported by controller (power-on default 03h) bit name r/w description 0 fan 1 = 1 r this bit set to 1 means the ADM1029 can support fan 1. 1 fan 2 = 1 r this bit set to 1 means the ADM1029 can support fan 2. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. register 03h ?fans supported in system (power-on default 0000 00?1) bit name r/w description 0 fan 1 = 1 r/w indicates that fan 1 is being used. set to 1 on power-up, but can be over- written by software. 1 fan 2 = ? r/w indicates that fan 2 is being used. set by pin 18 (tmin/install) on power-up, but can be overwritten by software. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C34C register 04h ?gpios supported by controller (power-on default 7fh) bit name r/w description 0 gpio 0 = 1 (pin 19) r this bit set to 1 means the ADM1029 can support gpio0, available on pin 19. 1 gpio 1 = 1 (pin 20) r this bit set to 1 means the ADM1029 can support gpio1, available on pin 20. 2 gpio 2 = 1 (pin 11) r this bit set to 1 means the ADM1029 can support gpio2, available on pin 11. 3 gpio 3 = 1 (pin 13) r this bit set to 1 means the ADM1029 can support gpio3, available on pin 13. 4 gpio 4 = 1 (pin 14) r this bit set to 1 means the ADM1029 can support gpio4, available on pin 14. 5 gpio 5 = 1 (pin 16) r this bit set to 1 means the ADM1029 can support gpio5, available on pin 16. 6 gpio 6 = 1 (pin 17) r this bit set to 1 means the ADM1029 can support gpio6, available on pin 17. 7 reserved r unused. will read back 0. register 06h ?temp devices installed (power-on default 0000 0??1) bit name r/w description 0 local temp = 1 r this bit is permanently set to 1 since the local temperature sensor is always available. 1 remote 1 temp = ? r this bit is set to 1 if the remote 1 temperature sensor (tdm1) is installed. (automatically detected on power-up.) 2 remote 2 temp = ? r this bit is set to 1 if the remote 2 temperature sensor (tdm2) is installed. (automatically detected on power-up.) 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C35C register 10h, 11h ?fan x * status (power-on default 0000 0?0?) bit name r/w description 0 missing = x r reflects the state of pins 4/21. low means fan x * is installed, high means it is missing. this bit will automatically return low if a missing fan is replaced. 1 missing _l = 0 r/w this bit is edge-triggered and latches a fan x * missing event on removal of fan x. this bit is cleared by writing a 0 to it. 2 fault_ = x r inverse of pin 2/23. low on pin means fan x * has a fault (pins 2/23 low), high on pin means it is ok. this bit will automatically return low if pins 2/23 goes high. 3 fault_l_ = 0 r/w this bit is edge-triggered and latches a fan x * fault event on pins 2/23. this bit is cleared by writing a 0 to it. if the present pin for a fan input is high (fan not installed) this bit will be cleared automatically. 4 sleep = 0 r/w when this bit is set, fan x * will be stopped and no fan x * faults will be monitored. if bit 4 in fan x * fault action register is set, fan x * will go to alarm speed if an overtemperature event is detected as per settings in the temp fault action registers. 5 hot plug priority r/w this bit indicates whether fan x runs at hot-plug speed (bit set to 1) or alarm speed (bit set to 0) if both modes are triggered. 6 tach_fault_l r/w latches a fan x tach fault. this bit is cleared by writing a 0 to it. if the present pin for a fan input is high (fan not installed), this bit will be cleared automatically. 7 hot_plug_l r/w this bit is edge-triggered and latches a fan x hot-plug event which is the insertion of fan x. (note difference to bit 1.) this bit is cleared by writ- ing a 0 to it. if a fan is hot-plug installed, it will run at normal speed. notes * x denotes the fan number. register 10h is for fan 1 and register 11h is for fan 2. question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C36C temperature registers register 06h ?temp devices installed (power-on default 0000 0??1) bit name r/w description 0 local temp = 1 r this bit is permanently set to 1 since the local temperature sensor is always available. 1 remote 1 temp = ? r this bit is set to 1 if the remote 1 temperature sensor (tdm1) is in stalled. (automatically detected on power-up.) 2 remote 2 temp = ? r this bit is set to 1 if the remote 2 temperature sensor (tdm2) is in stalled. (automatically detected on power-up.) 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. register 30h, 31h, 32h ?temp x * offset registers (power-on default 00h) bit name r/w description <7:0> offset r/w this register contains an offset value that is automatically added to the tem- perature value to reduce the effects of systemic offset errors. *x denotes the number of the temperature channel. register 30h is for local temperature channel, 31h is for remote 1 temp (d1) , 32h is for remote 2 temp (d2). register 40h, 41h, 42h ?temp x * fault action (power-on default 08h) bit name r/w description 0 assert cfault on r/w when this bit is set, cfault will be asserted when the temp x * tempera- ot = 0 ture exceeds the temp x * temperature high limit, not otherwise. 1 alarm speed on ot = 0 r/w when this bit is set, the fans(s) will go to alarm speed when the temp x * temperature exceeds the temp x * temperature high limit, not otherwise. 2 int on ot = 0 r/w when this bit is set, int will be asserted when the temp x * temperature exceeds the temp x * temperature high limit, not otherwise. 3 alarm below low = 0 r/w this bit indicates whether an alarm ( int , cfault , or alarm speed) is asserted when temperature goes above or below the low limit. 1 = above, 0 = below. this bit is set to 1 at power-up if automatic fan speed control is enabled by pin 18, cleared otherwise. 4 assert cfault on r/w when this bit is set, cfault will be asserted when the temp x * temperature ut = 0 crosses the temp x * temperature low limit, not otherwise. bit 3 decides whether cfault is asserted for going above or below the low limit. this bit is set to 1 if automatic fan speed control is enabled on power-up. 5 alarm speed on ut = 0 r/w when this bit is set, the fans(s) will go to alarm speed when the temp x * temperature crosses the temp x * temperature low limit, not otherwise. bit 3 decides whether alarm speed is asserted for going above or below the low limit. 6 int on ut = 0 r/w when this bit is set, int will be asserted when the temp x * temperature crosses the temp x * temperature low limit, not otherwise. bit 3 decides whether int is asserted for going above or below the low limit. 7 latch temp fault = 0 r/w this bit latches a temperature out-of-limit event (i.e., when the temperature goes above the high limit or crosses the low limit) on the temp x * channel. this bit is cleared by writing a 0 to it. * x denotes the number of the temperature channel. register 40h is for the local temperature channel, 41h is for remote 1 temp ( d1), 42h is for remote 2 temp (d2). rev. 0 ADM1029 C37C register 48h, 49h, 4ah ?temp x * cooling action (power-on default 00h) bit name r/w description 0 fan 1 = 0 r/w if a temp x * out-of-limit event is generated such that fans should be driven at alarm speed, fan 1 will be set to this speed when this bit is set. if no temp x * out-of-limit event is present, fan 1 will be set to the speed determined by the automatic fan speed control circuit as a result of temperature measurements on the temp x * channel when this bit is set. if this bit is not set, temp x * tem- perature measurements will have no effect on the speed of fan 1. 1 fan 2 = 0 r/w if a temp x * out-of-limit event is generated such that fans should be driven at alarm speed, fan 2 will be set to this speed when this bit is set. if no temp x * out-of-limit event is present, fan 2 will be set to the speed determined by the automatic fan speed control circuit as a result of temperature measure- ments on the temp x * channel when this bit is set. if this bit is not set, temp x tem perature measurements have no effect on the speed of fan 2. while in theory it is possible, through setting of bits 0 and 1 in registers 48h to 4ah, to have any temperature channel controlling any fan, in practice this is not feasible. a subset of possibilities only are supported as follows: case 1: tdm1 controlling fan 1 (bit 0 in 49h set and/or tdm2 controlling fan 2 bit 1 in 4ah set, only) case 2: local controlling fan 1 and/or fan 2 (bits 0, 1 in 48h only set) case 3: tdm1 controlling fan 1 and/or fan 2 (bits 0, 1 in 49h only set) case 4: tdm2 controlling fan 1 and/or fan 2 (bits 0, 1 in 4ah only set) case 5: fan 1 and/or fan 2 set to max speed (bits 0, 1 in 48h, 49h, (default) determined by temperature 4ah all set) measurements on all three channels. other: if bits 0,1 in registers 48h, 49h, 4ah are set inconsistent with these cases, fans will run at the speeds determined by the normal speed registers. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. * x denotes the number of the temperature channel. register 48h is for the local temperature channel. 49h is for remote 1 temp (d1), 4ah is for remote 2 temp (d2). rev. 0 ADM1029 C38C register 80h, 81h, 82h ?temp x * t min (power-on default 001??000) bit name r/w description <7:0> temp x * t min r/w this register contains the minimum temperature value for automatic fan speed control based on the temp x * temperature. on power-up pin 18 is sampled by the adc to determine the default value for temp x * t min . if pin 18 is strapped to gnd or v cc , this register defaults to 32 c, but automatic fan speed control is disabled. there are eight strappable options on pin 18. these options are used to set temp x * t min and the install bit in the config register (reg 01h, bit 0). the options are as follows: adc msbs r1 r2 install temp x * t min 111 0 1 disabled 101 18 k ? 82 k ? 148 c 110 22 k ? 47 k ? 140 c 100 12 k ? 15 k ? 132 c 011 15 k ? 12 k ? 032 c 010 47 k ? 22 k ? 040 c 001 82 k ? 18 k ? 048 c 000 0 0 disabled * x denotes the number of the temperature channel. register 80h is for the local temperature channel, 81h is for remote 1 temp (d1), 82h is for remote 2 temp (d2). register 88h, 89h, 8ah temp x * t range /t hyst (power-on default 51h) bit name r/w description <3:0> temp x * t range r/w this nibble contains the temperature range over which automatic fan speed control operates based on the temp x * measured temperature. only a limited number of temperature ranges are supported as follows: bits <3:0> t range 0000 5 c 0001 10 c 0010 20 c 0011 40 c 0100 80 c <7:4> temp x * t hyst r/w this nibble allows programmability of the hysteresis level around the temperature at which the fan being controlled by temp x * will switch on in automatic fan speed control mode. values from 0 c to 15 c are possible. if a value other than 0 c is programmed as a hysteresis value, the fan will switch on when temp x * goes above t min , but will remain on until temp x * falls below t min Ct hyst . between t min Ct hyst and t min the fan will run at the programmed minimum pulsewidth in the fan x * speed 1 register. * x denotes the number of the temperature channel. register 88h is for the local temperature channel , 89h is for remote 1 temp (d1), 8ah is for remote 2 temp (d2). rev. 0 ADM1029 C39C register 90h, 91h, 92h ?temp x * high limit (power-on default 80 c for local sensor, 100 c for remote sensors) bit name r/w description <7:0> temp x * high limit r/w this register contains the high limit value for the temp x * measurement. * x denotes the number of the temperature channel. register 90h is for the local temperature channel. 91h is for remote 1 temp ( d1), 92h is for remote 2 temp (d2). register 98h, 99h, 9ah ?temp x * low limit (power-on default 60 c for local sensor, 70 c for remote sensors) bit name r/w description <7:0> temp x * low limit r/w this register contains the low limit value for the temp x * measurement. * x denotes the number of the temperature channel. register 98h is for the local temperature channel. 99h is for remote 1 temp ( d1), 9ah is for remote 2 temp (d2). register a0h, a1h, a2h ?temp x * measured value (power-on default 00h) bit name r/w description <7:0> temp x * value r this register contains the actual temp x * measured value. * x denotes the number of the temperature channel. register a0h is for the local temperature channel. a1h is for remote 1 temp ( d1), a2h is for remote 2 temp (d2). rev. 0 ADM1029 C40C fan registers register 02h ?fan supported by controller (power-on default 03h) bit name r/w description 0 fan 1 = 1 r this bit set to 1 means the ADM1029 can support fan 1. 1 fan 2 = 1 r this bit set to 1 means the ADM1029 can support fan 2. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. register 03h ?fans supported in system (power-on default 0000 00?1) bit name r/w description 0 fan 1 = 1 r/w indicates that fan 1 is being used. set to 1 on power-up, but can be overwrit- ten by software. 1 fan 2 = ? r/w indicates that fan 2 is being used. set by pin 18 (tmin/install) on power-up, but can be overwritten by software. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. register 07h ?set fan x alarm speed (power-on default 00h) bit name r/w description 0 fan 1 alarm speed = 0 r/w when set to 1, fan 1 will run at alarm speed. 1 fan 2 alarm speed = 0 r/w when set to 1, fan 2 will run at alarm speed. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. register 08h ?set fan x hot-plug speed (power-on default 00h) bit name r/w description 0 fan 1 hot-plug speed = 0 r/w w hen set to 1, fan 1 will run at hot-plug speed. 1 fan 2 hot-plug speed = 0 r/w w hen set to 1, fan 2 will run at hot-plug speed. 2 0 r unused. will read back 0. 3 0 r unused. will read back 0. 4 0 r unused. will read back 0. 5 0 r unused. will read back 0. 6 0 r unused. will read back 0. 7 0 r unused. will read back 0. rev. 0 ADM1029 C41C register 09h ?set fan x full speed (power-on default 00h) bit name r/w description 0 fan 1 full speed = 0 r/w when set to 1 fan 1 will run at full speed. 1 fan 2 full speed = 0 r/w when set to 1 fan 2 will run at full speed. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. register 0ch ?fan spin-up register (power-on default 03h) bit name r/w description <7:4> reserved r unused 3 spin-up disable r/w when this bit is set to 1, fan spin-up to full speed will be disabled. <2:0> fan spin-up time r/w these bits select the spin-up time for the fans 000 = 16 seconds 001 = 8 seconds 010 = 4 seconds 011 = 2 seconds (default) 100 = 1 second 101 = 0.25 seconds 110 = 1/16 second 111 = 1/64 second register 10h, 11h ?fan x * status (power-on default 0000 0?0?) bit name r/w description 0 missing = x r reflects the state of pins 4/21. low means fan x * is installed, high means it is missing. this bit will automatically return low if a missing fan is replaced. 1 missing _l = 0 r/w this bit is edge-triggered and latches a fan x * missing event on removal of fan x * . this bit is cleared by writing a 0 to it. 2 fault_ = x r inverse of pin 2/23. low on pin means fan x * has a fault (pins 2/23 low), high on pin means it is ok. this bit will automatically return low if pin 2/23 goes high. 3 fault_l_ = 0 r/w this bit is edge-triggered and latches a fan x * fault event on pin 2/23. this bit is cleared by writing a 0 to it. if the present pin for a fan input is high (fan not installed) this bit will be cleared automatically. 4 sleep = 0 r/w when this bit is set, fan x * will be stopped and no fan x * faults will be monitored. if bit 4 in fan x * fault action register is set then fan x * will go to alarm speed if an overtemperature event is detected as per settings in the temp fault action registers. 5 hot plug priority r/w this bit indicates whether fan x * runs at hot-plug speed (bit set to 1) or alarm speed (bit set to 0) if both modes are triggered. 6 tach_fault_l r/w latches a fan x * tach fault. this bit is cleared by writing a 0 to it. if the present pin for a fan input is high (fan not installed) this bit w ill be cleared automatically. 7 hot_plug_l r/w this bit is edge-triggered and latches a fan x * hot-plug event which is the insertion of fan x * . (note difference to bit 1) this bit is cleared by writing a 0 to it. if a fan is hot-plug installed, it will run at normal speed. notes * x denotes the fan number. register 10h is for fan 1 and register 11h is for fan 2. question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C42C register 18h, 19h ?fan x * fault action (power-on default bfh) bit name r/w description 0 assert cfault on r/w if this bit is set, cfault will be asserted when there is a fault (tach or fault = 1 pins 2/23) on fan x * . 1 assert int on fault = 1 r/w if this bit is set, int will be asserted when there is a fault (tach or pins 2 23) on fan x * . 2 assert cfault on r/w if this bit is set, cfault will be asserted when there is a hot unplug event hot unplug = 1 on fan x * . 3 assert int on r/w if this bit is set, int will be asserted when there is a hot unplug event hot unplug = 1 on fan x * . 4 thermal override in r/w if bit 4 in fan x * status register is set then fan x * will go to alarm speed if sleep = 1 an overtemperature event is detected as per settings in temp x * fault action registers, while this bit is set. 5 drive fault_ on r/w if bit 3 or bit 6 of reg 10 is set, drive pins 2, 23 low if a fault is generated. fault_l = 1 6 hot-plug speed on r/w when this bit is set, fan x * will go to hot-plug speed when cfault is cfault in = 0 pulled low externally. 7 alarm on cfault = 1 r/w when this bit is set, fan x * will go to alarm speed when cfault is pulled low externally. * x denotes the fan number. register 18h is for fan 1 and register 19h is for fan 2. register 20h, 21h ?fan x * event mask (power-on default ffh) bit name r/w description 0 fan 1 = 1 r/w if a fault (tach or pins 2/23) is detected on fan x * , fan 1 will be driven to alarm speed when this bit is set. 1 fan 2 = 1 r/w if a fault (tach or pins 2/23) is detected on fan x * , fan 2 will be driven to alarm speed when this bit is set. 2 reserved r unused. will read back 1. 3 reserved r unused. will read back 1. 4 reserved r unused. will read back 1. 5 reserved r unused. will read back 1. 6 reserved r unused. will read back 1. 7 reserved r unused. will read back 1. * x denotes the fan number. register 20h is for fan 1 and register 21h is for fan 2. register 60h, 61h ?fan x * minimum/alarm speed (power-on default ffh) bit name r/w description 3C0 fan x minimum speed r/w this nibble contains the normal speed value for fan x * . when in automatic fan this nibble will contain the minimum speed at which fan x * will run. the power-up default for the min speed should be 5hex which corresponds to 33% pwm duty cycle. 7C4 fan x alarm speed r/w this nibble contains the alarm speed value for fan x * . * x denotes the fan number. register 60h is for fan 1 and 61h is for fan 2. rev. 0 ADM1029 C43C register 68h, 69h ?fan x * configuration (power-on default 2fh) bit name r/w description <3:0> fan x * hot-plug speed r/w this nibble contains the hot-plug speed value for fan x * . this is the speed the other fan(s) runs at if fan x * is hot-plug removed. if a fan is hot-plug installed, it will run at normal speed. <5:4> pwm frequency r/w these bits allow programmability of the nominal pwm frequency for fan x * . the following options are supported: bits 5C4 pwm freq 00 15.625 hz 01 62.5 hz 10 250 hz C default 11 1000 hz <7:6> oscillator frequency r/w these bits contain the oscillator frequency for the fan x * tach measurement. if set to 00, tach measurement is disabled for fan x * . bit 7 bit 6 oscillator frequency (hz) 0 0 measurement disabled 0 1 470 1 0 940 1 1 1880 * x denotes the fan number. register 68h is for fan 1 and 69h is for fan 2. register 70h, 71h ?fan x * tach value (power-on default 00h) bit name r/w description <7:0> fan x * tach value r this register contains the value of the fan x * tachometer measurement. * x denotes the fan number. register 70h is for fan 1 and 71h is for fan 2. register 78h, 79h ?fan x * tach high limit (power-on default ffh) bit name r/w description <7:0> fan x * tach high limit r/w this register contains the limit value for the fan x * tachometer measure- ment. since the tachometer circuit counts between tach pulses, a slow fan will result in a larger measured value, so exceeding the limit is the way to detect a slow or stopped fan. * x denotes the fan number. register 78h is for fan 1 and 79h is for fan 2. rev. 0 ADM1029 C44C gpio registers register 04h?pios supported by controller (power-on default 7fh) bit name r/w description 0 gpio 0 = 1 (pin 19) r this bit set to 1 means the ADM1029 can support gpio0, available on pin 19. 1 gpio 1 = 1 (pin 20) r this bit set to 1 means the ADM1029 can support gpio1, available on pin 20. 2 gpio 2 = 1 (pin 11) r this bit set to 1 means the ADM1029 can support gpio2, available on pin 11. 3 gpio 3 = 1 (pin 13) r this bit set to 1 means the ADM1029 can support gpio3, available on pin 13. 4 gpio 4 = 1 (pin 14) r this bit set to 1 means the ADM1029 can support gpio4, available on pin 14. 5 gpio 5 = 1 (pin 16) r this bit set to 1 means the ADM1029 can support gpio5, available on pin 16. 6 gpio 6 = 1 (pin 17) r this bit set to 1 means the ADM1029 can support gpio6, available on pin 17. 7 reserved r unused. will read back 0. register 05h?pio present/ain (power-on default 0????111) bit name r/w description 0 gpio 0 = 1 r/w indicates that gpio0 is being used. set to 1 on power-up, but can be over- written by software. setting this bit to 0 means ain0 is being used. 1 gpio 1 = 1 r/w indicates that gpio1 is being used. set to 1 on power-up, but can be over- written by software. setting this bit to 0 means ain1 is being used. 2 gpio 2 = 1 r/w indicates that gpio2 is being used. set to 1 on power-up, but can be over- written by software. 3 gpio 3 = ? r/w indicates that gpio3 is being used. setting this bit to 0 means tdm1 is being used. the ADM1029 can detect on power-up if tdm1 is connected. if so then this bit is set to 0, otherwise it is set to 1. the default setting can be overwritten by software. 4 gpio 4 = ? r/w indicates that gpio4 is being used. setting this bit to 0 means tdm1 is being used. the ADM1029 can detect on power-up if tdm1 is connected. if so then this bit is set to 0, otherwise it is set to 1. the default setting can be overwritten by software. 5 gpio 5 = ? r/w indicates that gpio5 is being used. setting this bit to 0 means tdm2 is being used. the ADM1029 can detect on power-up if tdm2 is connected. if so then this bit is set to 0, otherwise it is set to 1. the default setting can be overwritten by software. 6 gpio 6 = ? r/w indicates that gpio6 is being used. setting this bit to 0 means tdm2 is being used. the ADM1029 can detect on power-up if tdm2 is connected. if so then it is set to 1. the default setting can be overwritten by software. 7 reserved r unused. will read back 0. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. rev. 0 ADM1029 C45C register 28h, 29h, 2ah, 2bh, 2ch, 2dh, 2eh ?gpiox * behavior (power-on default 00h) bit name r/w description 0 direction = 0 r/w this bit indicates the direction for gpiox * pin. when set to 1 gpiox * will function as an input, when 0 gpiox * will function as an output. 1 polarity = 0 r/w this bit indicates the polarity of the gpiox * pin. when set to 1 gpiox * will be active high, when 0 gpiox * will be active low. 2 bit 2 = 0 r/w if gpiox * is configured as an input, cfault will be asserted if gpiox * pin is asserted while this bit is set. if gpio2 is configured as an output, gpio2 will be asserted if a temperature high limit is exceeded while this bit is set. if automatic fan speed control is enabled, this bit will be set by default. this can be used as a shutdown signal for a catastrophic overtemperature event. 3 bit 3 = 0 r/w if gpiox * is configured as an input, int will be asserted if gpiox * pin is asserted while this bit is set. if gpiox * is configured as an output, gpiox * will be asserted if a temperature low limit is exceeded while this bit is set. 4 bit 4 = 0 r/w if gpiox * is configured as an input, fans will go to alarm speed if gpiox * pin is asserted while this bit is set. if gpiox * is configured as an output, gpiox * will be asserted if a fan tach limit is exceeded while this bit is set. 5 bit 5 = 0 r/w if gpiox * is configured as an input, fans will go to hot-plug speed if gpiox * pin is asserted while this bit is set. if gpiox * is configured as an output, gpiox * will be asserted if a fan fault (pins 2/23) is detected while this bit is set. 6 bit 6 = 0 r if gpiox * is configured as an input, this bit will reflect state of gpiox * pin. r/w if gpiox * is configured as an output, gpiox will be asserted if an ain high limit is exceeded while this bit is set. 7 bit 7 = 0 r/w if gpiox * is configured as an input, this bit will latch a gpiox * assertion event. this bit is cleared by writing a 0 to it. if gpiox * is configured as an output, gpiox * will be asserted if an ain low limit is exceeded while this bit is set. * x denotes the number of the gpio pin. register 28h controls gpio0, 29h controls gpio1, etc. register 38h, 39h, 3ah, 3bh, 3ch, 3dh, 3eh ?gpiox * event mask (power-on default 00h) bit name r/w description 0 fan 1 = 0 r/w if gpiox * is asserted such that fans should be driven at alarm or hot-plug speed, fan 1 will be set to this speed when this bit is set. 1 fan 2 = 0 r/w if gpiox * is asserted such that fans should be driven at alarm or hot-plug speed, fan 2 will be set to this speed when this bit is set. 2 reserved r unused. will read back 0. 3 reserved r unused. will read back 0. 4 reserved r unused. will read back 0. 5 reserved r unused. will read back 0. 6 reserved r unused. will read back 0. 7 reserved r unused. will read back 0. * x denotes the number of the gpio pin. register 38h is for gpio0, 39h is for gpio1 etc. rev. 0 ADM1029 C46C ain registers register 05h ?gpio present/ain (power-on default 0????111) bit name r/w description 0 gpio 0 = 1 r/w indicates that gpio0 is being used. set to 1 on power-up, but can be over- written by software. setting this bit to 0 means ain0 is being used. 1 gpio 1 = 1 r/w indicates that gpio1 is being used. set to 1 on power-up, but can be over- written by software. setting this bit to 0 means ain1 is being used. 2 gpio 2 = 1 r/w indicates that gpio2 is being used. set to 1 on power-up, but can be over- written by software. 3 gpio 3 = ? r/w indicates that gpio3 is being used. setting this bit to 0 means tdm1 is being used. the ADM1029 can detect on power-up if tdm1 is connected. if so, this bit is set to 0; otherwise it is set to 1. the default setting can be overwrit- ten by software. 4 gpio 4 = ? r/w indicates that gpio4 is being used. setting this bit to 0 means tdm1 is being used. the ADM1029 can detect on power-up if tdm1 is connected. if so, this bit is set to 0; otherwise it is set to 1. the default setting can be overwrit- ten by software. 5 gpio 5 = ? r/w indicates that gpio5 is being used. setting this bit to 0 means tdm2 is being used. the ADM1029 can detect on power-up if tdm2 is connected. if so, this bit is set to 0; otherwise it is set to 1. the default setting can be overwrit- ten by software. 6 gpio 6 = ? r/w indicates that gpio6 is being used. setting this bit to 0 means tdm2 is being used. the ADM1029 can detect on power-up if tdm2 is connected. if so, this bit is set to 0; otherwise it is set to 1. the default setting can be overwrit- ten by software. 7 reserved r unused. will read back 0. note question marks on this and following pages indicate bit settings that depend on the state of certain pins on power-up. register 50h, 51h ?ainx * behavior (power-on default 00h) bit name r/w description 0 assert cfault on r/w when this bit is set, cfault is asserted when ainx * exceeds the ainx * hi_lim = 0 high limit. 1 alarm speed on r/w when this bit is set, the fans go to alarm speed when ainx * exceeds the hi_lim = 0 ainx * high limit. 2 int on hi_lim = 0 r/w when this bit is set, int is asserted when ainx * exceeds the ainx * high limit. 3 alarm below low = 0 r/w this bit indicates whether an alarm ( int , cfault or alarm speed) is asserted when ainx * goes above or below the low limit. 1 = above. 0 = below. 4 assert cfault on r/w when this bit is set, cfault is asserted when ainx * crosses the ainx * lo_lim = 0 low limit. bit 3 decides whether cfault is asserted for going above or below the low limit. 5 alarm speed on r/w when this bit is set, the fans go to alarm speed when ainx * crosses the ainx * lo_lim = 0 low limit. bit 3 decides whether alarm speed is asserted for going above or below the low limit. 6 int on lo_lim = 0 r/w when this bit is set, int is asserted when ainx * crosses the ainx * low limit. bit 3 decides whether int is asserted for going above or below the low limit. 7 latch ain fault = 0 r/w this bit latches an out-of-limit event (i.e., when ainx * goes above the high limit or crosses the low limit) on the ainx * channel. this bit is cleared by writing a 0 to it. * x denotes the number of the ain channel. register 50h controls ain0 and 51h controls ain1. rev. 0 ADM1029 C47C register 58h, 59h ?ainx * event mask (power-on default 00h) bit name r/w description 0 fan 1 = 0 r/w if an ainx * out-of-limit event is generated such that fans should be driven at alarm speed, fan 1 will be set to this speed when this bit is set. 1 fan 2 = 0 r/w if an ainx * out-of-limit event is generated such that fans should be driven at alarm speed, fan 2 will be set to this speed when this bit is set. 2 reserved r/w undefined 3 reserved r/w undefined 4 reserved r/w undefined 5 reserved r/w undefined 6 reserved r/w undefined 7 reserved r/w undefined * x denotes the number of the ain channel. register 58h is for ain0 and 59h is for ain1. register a8h, a9h ?ainx * high limit (power-on default ffh) bit name r/w description <7:0> ainx * high limit r/w this register contains the high limit value for the ainx * analog input channel. * x denotes the number of the ain channel. register a8h is for ain0 and a9h is for ain1. register b0h, b1h ?ainx * low limit (power-on default 00h) bit name r/w description <7:0> ainx * low limit r/w this register contains the low limit value for the ainx * analog input channel. * x denotes the number of the ain channel. register b0h is for ain0 and b1h is for ain1. register b8h, b9h ?ainx * measured value (power-on default 00h) bit name r/w description <7:0> ainx * value r this register contains the measured value of the ainx * analog input channel. * x denotes the number of the ain channel. register b8h is for ain0 and b9h is for ain1. rev. 0 C48C c01721C1C7/01(0) printed in u.s.a. ADM1029 miscellaneous registers register 0bh ?s/w reset (power-on default 00h) bit name r/w description <7:0> s/w reset r/w writing a6 hex to this register location causes a software reset identical to a power-on reset. this register is self-clearing so reading from it after the soft- ware reset has completed will result in 00 hex being read. register 0dh ?manufacturer? id (power-on default 41h) bit name r/w description <7:0> manufacturers id code r this register contains the manufacturers id code for the device. register 0eh ?revision (power-on default 00h) bit name r/w description <3:0> minor revision code r t his nibble contains the manufacturers code for minor revisions to the device. <7:4> major revision code r this nibble contains the manufacturers code for major revisions to the device which would likely require a s/w revision. register 0fh ?manufacturer? test register (power-on default 00h) bit name r/w description <7:0> manufacturers test r/w this register is used by the manufacturer for test purposes. it should not be read from or written to in normal operation. outline dimensions dimensions shown in inches and (mm). 24-lead qsop package (rq-24) 24 13 12 1 0.337 (8.74) 0.334 (8.56) 0.244 (6.20) 0.228 (5.79) pin 1 0.157 (3.99) 0.150 (3.81) seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.059 (1.50) max 0.069 (1.75) 0.053 (1.35) 0.010 (0.20) 0.007 (0.18) 0.050 (1.27) 0.016 (0.41) 8 0 |
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